Message ID | 20201204222622.2743175-6-f4bug@amsat.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | mips: Sanitize Multi-Threading ASE | expand |
On 12/4/20 4:26 PM, Philippe Mathieu-Daudé wrote: > PTC field has 8 bits, PVPE has 4. We plan to use the > "hw/registerfields.h" API with MIPS CPU definitions > (target/mips/cpu.h). Meanwhile we use magic 8 and 4. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > We want to move that to mips_cpu_reset() later, > because this is not Malta specific but cpu-specific. > However SMP 'cpus' come from MachineState ("hw/boards.h"). > So meanwhile this is early review. > --- > hw/mips/malta.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 350b92b4d79..c35fbf97272 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/bitops.h" #include "qemu-common.h" #include "cpu.h" #include "hw/clock.h" @@ -1135,8 +1136,11 @@ static void malta_mips_config(MIPSCPU *cpu) CPUState *cs = CPU(cpu); if (ase_mt_available(env)) { - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | - ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PTC, 8, + smp_cpus * cs->nr_threads - 1); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PVPE, 4, smp_cpus - 1); } }
PTC field has 8 bits, PVPE has 4. We plan to use the "hw/registerfields.h" API with MIPS CPU definitions (target/mips/cpu.h). Meanwhile we use magic 8 and 4. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- We want to move that to mips_cpu_reset() later, because this is not Malta specific but cpu-specific. However SMP 'cpus' come from MachineState ("hw/boards.h"). So meanwhile this is early review. --- hw/mips/malta.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)