Message ID | 20201218060114.3591217-20-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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18 Dec 2020 14:06:34 +0800 IronPort-SDR: SVGDUY3vNJasOnlEMA6e39MboDFFo3ittDTTYO73uPHaY/VHTmEBtt0sq0Xqoi0hJo3s8Jaw5W rFu1JQ0cCFeQUyYSYdTh4hxB8N4/wOESyYBslOXAHt7qCVNUU7NSID0806w+GIMIHO/+8mBRtk wjQNXVDhLjCa1u+nSvAI7yeoYW5B4etEwe95BkObPvtGEa73lTyHd3MNgkbu7guMGsWaJ51VcU ZrrjIipDXbD4IrDEBH3RB1pWSyj+41bqSoocQXE2ZdfYFUpPu2vQ3qWg5n1izdAx48TJE/Gu3H M2gCShKKmb27JlIZyLq+qk2d Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 21:46:41 -0800 IronPort-SDR: fhfo9Z0lvm6mIMSsNsUmIPqs3w95I02CssDM9KHZflTq3WwrY6vArHw0I7epBHWMTnDjZxjYOC BYcbffjdBIf/LgpDimjPn06CGsfiac4AA2w5betMaC9gYoyCGd076+bL1VVtVbUn6PaNkrqfzC a9cGvak7Wmf+caBLg6afGVebRRmHazfTHVpmcuVhjiqV7795dnNjKtoyoZdnZJGuZoHr2VFq6h UXSBWHdgR/Dv3Ky2amTBzwNMCZko8IC1O7tvXmzGgTDjzP2HcniHvR0ettbZWCFF79F9lb2RKv FOA= WDCIronportException: Internal Received: from 6hj08h2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.68]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Dec 2020 22:01:25 -0800 From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks Date: Thu, 17 Dec 2020 22:01:10 -0800 Message-Id: <20201218060114.3591217-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218060114.3591217-1-alistair.francis@wdc.com> References: <20201218060114.3591217-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=68.232.143.124; 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[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
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diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7274f971a4..a2afb95fa1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -447,11 +447,13 @@ restart: return TRANSLATE_PMP_FAIL; } -#if defined(TARGET_RISCV32) - target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); -#elif defined(TARGET_RISCV64) - target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); -#endif + target_ulong pte; + if (riscv_cpu_is_32bit(env)) { + pte = address_space_ldl(cs->as, pte_addr, attrs, &res); + } else { + pte = address_space_ldq(cs->as, pte_addr, attrs, &res); + } + if (res != MEMTX_OK) { return TRANSLATE_FAIL; }