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17 Dec 2020 21:46:35 -0800 IronPort-SDR: 2KdFiPxvMSV91NlUmU22nYMS/uI29euUS36CnpQEL9fPKnDpacE6QEIrWkH1rx83/AZ7QcCQ3M 0mfPZ60bIW3O2r594PLW2VN8aANuhsxaqHL/6IvRcupM7OHdHTT6Vv9Ed0I4rkJujeB8+SbUwu LVC+2Q9IR5nbWEOb0I4bpKjI1QNEeIhxktHs7S4wkCfI4KFk7R55y5LI/LwtVN7+ZSg+sjzufe ga/mvLPyBaD7plrwYxxbQQwxeId+77sWSkDEeh+NFuARjvk11p+IMf/aVHEGHTLue2oF5JSya/ 3fU= WDCIronportException: Internal Received: from 6hj08h2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.68]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Dec 2020 22:01:19 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process Date: Thu, 17 Dec 2020 22:00:57 -0800 Message-Id: <20201218060114.3591217-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218060114.3591217-1-alistair.francis@wdc.com> References: <20201218060114.3591217-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=614e9c0eb=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , Jackie Ke Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Previously if an interrupt occured during the claim process (after the interrupt is claimed but before it's completed) it would never be cleared. This patch ensures that we also clear the hidden_pending bits as well. Signed-off-by: Alistair Francis Tested-by: Jackie Ke Message-id: 4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com --- hw/intc/ibex_plic.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 341c9db405..c1b72fcab0 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -43,16 +43,23 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level) { int pending_num = irq / 32; + if (!level) { + /* + * If the level is low make sure we clear the hidden_pending. + */ + s->hidden_pending[pending_num] &= ~(1 << (irq % 32)); + } + if (s->claimed[pending_num] & 1 << (irq % 32)) { /* * The interrupt has been claimed, but not completed. * The pending bit can't be set. + * Save the pending level for after the interrupt is completed. */ s->hidden_pending[pending_num] |= level << (irq % 32); - return; + } else { + s->pending[pending_num] |= level << (irq % 32); } - - s->pending[pending_num] |= level << (irq % 32); } static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)