diff mbox series

[PULL,20/22] ppc440_pcix: Improve comment for IRQ mapping

Message ID 20210106033816.232598-21-david@gibson.dropbear.id.au (mailing list archive)
State New, archived
Headers show
Series [PULL,01/22] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code | expand

Commit Message

David Gibson Jan. 6, 2021, 3:38 a.m. UTC
From: BALATON Zoltan via <qemu-ppc@nongnu.org>

The code mapping all PCI interrupts to a single CPU IRQ works but is
not trivial so document it in a comment.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <c25c0310510672b58466e795fd701e65e8f1ff97.1609636173.git.balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
 hw/ppc/ppc440_pcix.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)
diff mbox series


diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index ee952314c8..eb1290ffc8 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -415,8 +415,15 @@  static void ppc440_pcix_reset(DeviceState *dev)
     s->sts = 0;
-/* All pins from each slot are tied to a single board IRQ.
- * This may need further refactoring for other boards. */
+ * All four IRQ[ABCD] pins from all slots are tied to a single board
+ * IRQ, so our mapping function here maps everything to IRQ 0.
+ * The code in pci_change_irq_level() tracks the number of times
+ * the mapped IRQ is asserted and deasserted, so if multiple devices
+ * assert an IRQ at the same time the behaviour is correct.
+ *
+ * This may need further refactoring for boards that use multiple IRQ lines.
+ */
 static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
     trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);