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[PULL,03/23] target/arm: Fix MTE0_ACTIVE

Message ID 20210108153621.3868-4-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show
Series [PULL,01/23] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs | expand

Commit Message

Peter Maydell Jan. 8, 2021, 3:36 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

In 50244cc76abc we updated mte_check_fail to match the ARM
pseudocode, using the correct EL to select the TCF field.
But we failed to update MTE0_ACTIVE the same way, which led
to g_assert_not_reached().

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1907137
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201221204426.88514-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2d0d4cd1e10..d077dd9ef51 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12928,7 +12928,7 @@  static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
             && tbid
             && !(env->pstate & PSTATE_TCO)
-            && (sctlr & SCTLR_TCF0)
+            && (sctlr & SCTLR_TCF)
             && allocation_tag_access_enabled(env, 0, sctlr)) {
             flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
         }