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Fri, 08 Jan 2021 14:52:37 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h16sm14296297wrq.29.2021.01.08.14.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 14:52:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B7E911FF9F; Fri, 8 Jan 2021 22:42:58 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v1 17/20] riscv: Add semihosting support for user mode Date: Fri, 8 Jan 2021 22:42:53 +0000 Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , =?utf-8?q?Alex_Benn=C3=A9e?= , Keith Packard , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Kito Cheng This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Reviewed-by: Keith Packard Message-Id: <20210107170717.2098982-7-keithp@keithp.com> Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- linux-user/riscv/cpu_loop.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437875..9665dabb09 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP;