| Message ID | 20210109233427.749748-1-f4bug@amsat.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/i386: Use X86Seg enum for segment registers | expand |
On 1/9/21 1:34 PM, Philippe Mathieu-Daudé wrote: > Use the dedicated X86Seg enum type for segment registers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/i386/cpu.h | 4 ++-- > target/i386/gdbstub.c | 2 +- > target/i386/tcg/seg_helper.c | 8 ++++---- > target/i386/tcg/translate.c | 6 +++--- > 4 files changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 10/01/21 00:34, Philippe Mathieu-Daudé wrote: > Use the dedicated X86Seg enum type for segment registers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/i386/cpu.h | 4 ++-- > target/i386/gdbstub.c | 2 +- > target/i386/tcg/seg_helper.c | 8 ++++---- > target/i386/tcg/translate.c | 6 +++--- > 4 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index af130512e22..d23a5b340a8 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1807,7 +1807,7 @@ void cpu_sync_bndcs_hflags(CPUX86State *env); > /* this function must always be used to load data in the segment > cache: it synchronizes the hflags with the segment cache values */ > static inline void cpu_x86_load_seg_cache(CPUX86State *env, > - int seg_reg, unsigned int selector, > + X86Seg seg_reg, unsigned int selector, > target_ulong base, > unsigned int limit, > unsigned int flags) > @@ -1896,7 +1896,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, > /* cpu-exec.c */ > /* the following helpers are only usable in user mode simulation as > they can trigger unexpected exceptions */ > -void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); > +void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); > void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); > void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); > void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); > diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c > index 4a3de5f69da..41e265fc67a 100644 > --- a/target/i386/gdbstub.c > +++ b/target/i386/gdbstub.c > @@ -232,7 +232,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > return 0; > } > > -static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf) > +static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) > { > CPUX86State *env = &cpu->env; > uint16_t selector = ldl_p(mem_buf); > diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c > index 5f2ee6aa7ea..180d47f0e9b 100644 > --- a/target/i386/tcg/seg_helper.c > +++ b/target/i386/tcg/seg_helper.c > @@ -176,8 +176,8 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, > } > } > > -static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl, > - uintptr_t retaddr) > +static void tss_load_seg(CPUX86State *env, X86Seg seg_reg, int selector, > + int cpl, uintptr_t retaddr) > { > uint32_t e1, e2; > int rpl, dpl; > @@ -2098,7 +2098,7 @@ void helper_iret_real(CPUX86State *env, int shift) > env->hflags2 &= ~HF2_NMI_MASK; > } > > -static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) > +static inline void validate_seg(CPUX86State *env, X86Seg seg_reg, int cpl) > { > int dpl; > uint32_t e2; > @@ -2623,7 +2623,7 @@ void helper_verw(CPUX86State *env, target_ulong selector1) > } > > #if defined(CONFIG_USER_ONLY) > -void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) > +void cpu_x86_load_seg(CPUX86State *env, X86Seg seg_reg, int selector) > { > if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { > int dpl = (env->eflags & VM_MASK) ? 3 : 0; > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > index 11db2f3c8d2..6a4c31f933b 100644 > --- a/target/i386/tcg/translate.c > +++ b/target/i386/tcg/translate.c > @@ -2287,13 +2287,13 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, > } > } > > -static inline void gen_op_movl_T0_seg(DisasContext *s, int seg_reg) > +static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) > { > tcg_gen_ld32u_tl(s->T0, cpu_env, > offsetof(CPUX86State,segs[seg_reg].selector)); > } > > -static inline void gen_op_movl_seg_T0_vm(DisasContext *s, int seg_reg) > +static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) > { > tcg_gen_ext16u_tl(s->T0, s->T0); > tcg_gen_st32_tl(s->T0, cpu_env, > @@ -2303,7 +2303,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, int seg_reg) > > /* move T0 to seg_reg and compute if the CPU state may change. Never > call this function with seg_reg == R_CS */ > -static void gen_movl_seg_T0(DisasContext *s, int seg_reg) > +static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) > { > if (s->pe && !s->vm86) { > tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); > Queued, thanks. Paolo
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af130512e22..d23a5b340a8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1807,7 +1807,7 @@ void cpu_sync_bndcs_hflags(CPUX86State *env); /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ static inline void cpu_x86_load_seg_cache(CPUX86State *env, - int seg_reg, unsigned int selector, + X86Seg seg_reg, unsigned int selector, target_ulong base, unsigned int limit, unsigned int flags) @@ -1896,7 +1896,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, /* cpu-exec.c */ /* the following helpers are only usable in user mode simulation as they can trigger unexpected exceptions */ -void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); +void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4a3de5f69da..41e265fc67a 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -232,7 +232,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } -static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf) +static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) { CPUX86State *env = &cpu->env; uint16_t selector = ldl_p(mem_buf); diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 5f2ee6aa7ea..180d47f0e9b 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -176,8 +176,8 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, } } -static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl, - uintptr_t retaddr) +static void tss_load_seg(CPUX86State *env, X86Seg seg_reg, int selector, + int cpl, uintptr_t retaddr) { uint32_t e1, e2; int rpl, dpl; @@ -2098,7 +2098,7 @@ void helper_iret_real(CPUX86State *env, int shift) env->hflags2 &= ~HF2_NMI_MASK; } -static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) +static inline void validate_seg(CPUX86State *env, X86Seg seg_reg, int cpl) { int dpl; uint32_t e2; @@ -2623,7 +2623,7 @@ void helper_verw(CPUX86State *env, target_ulong selector1) } #if defined(CONFIG_USER_ONLY) -void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) +void cpu_x86_load_seg(CPUX86State *env, X86Seg seg_reg, int selector) { if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { int dpl = (env->eflags & VM_MASK) ? 3 : 0; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 11db2f3c8d2..6a4c31f933b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2287,13 +2287,13 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, } } -static inline void gen_op_movl_T0_seg(DisasContext *s, int seg_reg) +static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) { tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State,segs[seg_reg].selector)); } -static inline void gen_op_movl_seg_T0_vm(DisasContext *s, int seg_reg) +static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) { tcg_gen_ext16u_tl(s->T0, s->T0); tcg_gen_st32_tl(s->T0, cpu_env, @@ -2303,7 +2303,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, int seg_reg) /* move T0 to seg_reg and compute if the CPU state may change. Never call this function with seg_reg == R_CS */ -static void gen_movl_seg_T0(DisasContext *s, int seg_reg) +static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { if (s->pe && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
Use the dedicated X86Seg enum type for segment registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/i386/cpu.h | 4 ++-- target/i386/gdbstub.c | 2 +- target/i386/tcg/seg_helper.c | 8 ++++---- target/i386/tcg/translate.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-)