@@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
@@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+cpop 011000 000010 ..... 001 ..... 0010011 @r2
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, gen_ctz);
}
+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
return gen_unary(ctx, a, gen_ctzw);
}
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_cpopw);
+}
+
#endif
@@ -726,6 +726,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_i64(ret, ret, 32);
}
+static void gen_cpopw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,