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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id h16sm2865664pgd.62.2021.01.12.01.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 01:44:34 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs Date: Tue, 12 Jan 2021 17:39:41 +0800 Message-Id: <20210112093950.17530-68-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com> References: <20210112093950.17530-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/csr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 28c1ce7928a..176010674e8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -301,7 +301,7 @@ static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return -1; } - env->mstatus |= MSTATUS_VS; + env->mstatus |= MSTATUS_VS | MSTATUS_SD; #endif env->vxrm = val; @@ -320,7 +320,7 @@ static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return -1; } - env->mstatus |= MSTATUS_VS; + env->mstatus |= MSTATUS_VS | MSTATUS_SD; #endif env->vxsat = val; @@ -339,7 +339,7 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return -1; } - env->mstatus |= MSTATUS_VS; + env->mstatus |= MSTATUS_VS | MSTATUS_SD; #endif /* @@ -362,7 +362,7 @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return -1; } - env->mstatus |= MSTATUS_VS; + env->mstatus |= MSTATUS_VS | MSTATUS_SD; #endif env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;