@@ -310,6 +310,8 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
CPUState *cpu = CPU(dev);
Object *machine = qdev_get_machine();
+ qemu_init_vcpu(cpu);
+
/* qdev_get_machine() can return something that's not TYPE_MACHINE
* if this is one of the user-only emulators; in that case there's
* no need to check the ignore_memory_transaction_failures board flag.
@@ -56,18 +56,15 @@ static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
- qemu_init_vcpu(cs);
-
acc->parent_realize(dev, errp);
}
@@ -1864,10 +1864,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
acc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
@@ -98,10 +98,9 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void avr_cpu_set_int(void *opaque, int irq, int level)
@@ -135,8 +135,6 @@ static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
ccc->parent_realize(dev, errp);
}
@@ -102,7 +102,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
acc->parent_realize(dev, errp);
#ifndef CONFIG_USER_ONLY
@@ -6484,8 +6484,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
mce_init(cpu);
- qemu_init_vcpu(cs);
-
+ xcc->parent_realize(dev, &local_err);
/*
* Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
* fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
@@ -6512,8 +6511,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- xcc->parent_realize(dev, &local_err);
-
out:
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -133,9 +133,6 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
-
- qemu_init_vcpu(cs);
-
lcc->parent_realize(dev, errp);
}
@@ -248,8 +248,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
m68k_cpu_init_gdb(cpu);
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
mcc->parent_realize(dev, errp);
}
@@ -146,15 +146,14 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
uint8_t version_code = 0;
const char *version;
int i = 0;
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
@@ -166,7 +165,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
+ mcc->parent_realize(dev, errp);
version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
for (i = 0; mb_cpu_lookup[i].name && version; i++) {
@@ -232,8 +231,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->cfg.mmu_tlb_access = 3;
cpu->cfg.mmu_zones = 16;
cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
-
- mcc->parent_realize(dev, errp);
}
static void mb_cpu_initfn(Object *obj)
@@ -425,8 +425,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
mvp_init(env);
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
mcc->parent_realize(dev, errp);
}
@@ -66,10 +66,8 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void moxie_cpu_initfn(Object *obj)
@@ -121,10 +121,8 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
ncc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
@@ -105,10 +105,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
occ->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void openrisc_cpu_initfn(Object *obj)
@@ -372,7 +372,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
-static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+static void riscv_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(dev);
@@ -517,10 +517,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_cpu_register_gdb_regs_for_features(cs);
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
mcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void riscv_cpu_init(Object *obj)
@@ -578,7 +576,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
- device_class_set_parent_realize(dc, riscv_cpu_realize,
+ device_class_set_parent_realize(dc, riscv_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
@@ -106,7 +106,7 @@ static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
return oc;
}
-static void rx_cpu_realize(DeviceState *dev, Error **errp)
+static void rx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
@@ -118,10 +118,8 @@ static void rx_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
- cpu_reset(cs);
-
rcc->parent_realize(dev, errp);
+ cpu_reset(cs);
}
static void rx_cpu_set_irq(void *opaque, int no, int request)
@@ -192,7 +190,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
CPUClass *cc = CPU_CLASS(klass);
RXCPUClass *rcc = RX_CPU_CLASS(klass);
- device_class_set_parent_realize(dc, rx_cpu_realize,
+ device_class_set_parent_realize(dc, rx_cpu_realizefn,
&rcc->parent_realize);
device_class_set_parent_reset(dc, rx_cpu_reset,
&rcc->parent_reset);
@@ -232,8 +232,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
#endif
s390_cpu_gdb_init(cs);
- qemu_init_vcpu(cs);
+ scc->parent_realize(dev, &err);
/*
* KVM requires the initial CPU reset ioctl to be executed on the target
* CPU thread. CPU hotplug under single-threaded TCG will not work with
@@ -246,7 +246,6 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
cpu_reset(cs);
}
- scc->parent_realize(dev, &err);
out:
error_propagate(errp, err);
}
@@ -186,8 +186,6 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
scc->parent_realize(dev, errp);
}
@@ -739,9 +739,9 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
- Error *local_err = NULL;
SPARCCPU *cpu = SPARC_CPU(dev);
CPUSPARCState *env = &cpu->env;
+ Error *local_err = NULL;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
@@ -769,8 +769,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- qemu_init_vcpu(cs);
-
scc->parent_realize(dev, errp);
}
@@ -93,8 +93,6 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
tcc->parent_realize(dev, errp);
}
@@ -93,8 +93,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
set_feature(env, TRICORE_FEATURE_13);
}
cpu_reset(cs);
- qemu_init_vcpu(cs);
-
tcc->parent_realize(dev, errp);
}
@@ -84,18 +84,14 @@ static void uc32_any_cpu_initfn(Object *obj)
static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
{
- CPUState *cs = CPU(dev);
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- cpu_exec_realizefn(cs, &local_err);
+ cpu_exec_realizefn(CPU(dev), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
-
- qemu_init_vcpu(cs);
-
ucc->parent_realize(dev, errp);
}
@@ -153,8 +153,6 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
- qemu_init_vcpu(cs);
-
xcc->parent_realize(dev, errp);
}
@@ -10093,7 +10093,7 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
return 0;
}
-static void ppc_cpu_realize(DeviceState *dev, Error **errp)
+static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
@@ -10143,7 +10143,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
pcc->gdb_num_sprs, "power-spr.xml", 0);
#endif
- qemu_init_vcpu(cs);
pcc->parent_realize(dev, errp);
@@ -10850,7 +10849,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
- device_class_set_parent_realize(dc, ppc_cpu_realize,
+ device_class_set_parent_realize(dc, ppc_cpu_realizefn,
&pcc->parent_realize);
device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
&pcc->parent_unrealize);
move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. Despite this, the way cpu realize is done continues to be not ideal; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid even more redundant open coded additional calls in target/xxx/cpu.c, but this cannot happen because target cpu code, plugins, etc now all came to rely on cpu->index (which is updated in cpu_list_add), since no particular order was defined previously, so we are stuck with the freak call order for the target cpu realizefn. After this patch the target/xxx/cpu.c realizefn body becomes: void mycpu_realizefn(DeviceState *dev, Error **errp) { /* ... */ cpu_exec_realizefn(CPU_STATE(dev), errp); /* ... anything that needs done pre-qemu_vcpu_init */ xcc->parent_realize(dev, errp); /* does qemu_vcpu_init */ /* ... anything that needs to be done after qemu_vcpu_init */ } Signed-off-by: Claudio Fontana <cfontana@suse.de> --- hw/core/cpu.c | 2 ++ target/alpha/cpu.c | 5 +---- target/arm/cpu.c | 4 +--- target/avr/cpu.c | 3 +-- target/cris/cpu.c | 2 -- target/hppa/cpu.c | 1 - target/i386/cpu.c | 5 +---- target/lm32/cpu.c | 3 --- target/m68k/cpu.c | 2 -- target/microblaze/cpu.c | 9 +++------ target/mips/cpu.c | 2 -- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 4 +--- target/openrisc/cpu.c | 4 +--- target/riscv/cpu.c | 8 +++----- target/rx/cpu.c | 8 +++----- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 2 -- target/sparc/cpu.c | 4 +--- target/tilegx/cpu.c | 2 -- target/tricore/cpu.c | 2 -- target/unicore32/cpu.c | 6 +----- target/xtensa/cpu.c | 2 -- target/ppc/translate_init.c.inc | 5 ++--- 24 files changed, 23 insertions(+), 69 deletions(-)