diff mbox series

[4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree

Message ID 20210112215504.2093955-5-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/mips: Convert Loongson LEXT opcodes to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Jan. 12, 2021, 9:55 p.m. UTC 
Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
(divide 64-bit unsigned integers) opcodes to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/godson2.decode    |  2 ++
 target/mips/loong-ext.decode  |  2 ++
 target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
 target/mips/translate.c       | 37 -----------------------
 4 files changed, 59 insertions(+), 37 deletions(-)

Comments

Richard Henderson Jan. 21, 2021, 7:58 p.m. UTC | #1 
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
> (divide 64-bit unsigned integers) opcodes to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/godson2.decode    |  2 ++
>  target/mips/loong-ext.decode  |  2 ++
>  target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
>  target/mips/translate.c       | 37 -----------------------
>  4 files changed, 59 insertions(+), 37 deletions(-)
> 
> diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
> index b56a93a1999..0d5a72064d2 100644
> --- a/target/mips/godson2.decode
> +++ b/target/mips/godson2.decode
> @@ -14,4 +14,6 @@
>  @rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &muldiv
>  
>  DIV.G           011111 ..... ..... ..... 00000 011010   @rs_rt_rd
> +DIVU.G          011111 ..... ..... ..... 00000 011011   @rs_rt_rd
>  DDIV.G          011111 ..... ..... ..... 00000 011110   @rs_rt_rd
> +DDIVU.G         011111 ..... ..... ..... 00000 011111   @rs_rt_rd
> diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
> index 331c2226ae3..2e98262b81d 100644
> --- a/target/mips/loong-ext.decode
> +++ b/target/mips/loong-ext.decode
> @@ -16,3 +16,5 @@
>  
>  DIV.G           011100 ..... ..... ..... 00000 010100   @rs_rt_rd
>  DDIV.G          011100 ..... ..... ..... 00000 010101   @rs_rt_rd
> +DIVU.G          011100 ..... ..... ..... 00000 010110   @rs_rt_rd
> +DDIVU.G         011100 ..... ..... ..... 00000 010111   @rs_rt_rd
> diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
> index 634d4ba8031..7b3304ec749 100644
> --- a/target/mips/loong_translate.c
> +++ b/target/mips/loong_translate.c
> @@ -92,6 +92,61 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
>      return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
>  }
>  
> +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
> +                            bool is_double)
> +{
> +    TCGv t0, t1;
> +    TCGLabel *l1, *l2;
> +
> +    if (is_double) {
> +        if (TARGET_LONG_BITS != 64) {
> +            return false;
> +        }
> +        check_mips_64(s);
> +    }
> +
> +    if (rd == 0) {
> +        /* Treat as NOP. */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_local_new();
> +    t1 = tcg_temp_local_new();
> +    l1 = gen_new_label();
> +    l2 = gen_new_label();
> +
> +    gen_load_gpr(t0, rs);
> +    gen_load_gpr(t1, rt);
> +
> +    if (!is_double) {
> +        tcg_gen_ext32u_tl(t0, t0);
> +        tcg_gen_ext32u_tl(t1, t1);
> +    }
> +    tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
> +    tcg_gen_movi_tl(cpu_gpr[rd], 0);
> +
> +    tcg_gen_br(l2);
> +    gen_set_label(l1);
> +    tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
> +    tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);

this extend should be conditional on !is_double.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Philippe Mathieu-Daudé Aug. 10, 2021, 5:51 a.m. UTC | #2 
On 1/21/21 8:58 PM, Richard Henderson wrote:
> On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
>> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
>> (divide 64-bit unsigned integers) opcodes to decodetree.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>  target/mips/godson2.decode    |  2 ++
>>  target/mips/loong-ext.decode  |  2 ++
>>  target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
>>  target/mips/translate.c       | 37 -----------------------
>>  4 files changed, 59 insertions(+), 37 deletions(-)

>> +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
>> +                            bool is_double)
>> +{
>> +    TCGv t0, t1;
>> +    TCGLabel *l1, *l2;
>> +
>> +    if (is_double) {
>> +        if (TARGET_LONG_BITS != 64) {
>> +            return false;
>> +        }
>> +        check_mips_64(s);
>> +    }
>> +
>> +    if (rd == 0) {
>> +        /* Treat as NOP. */
>> +        return true;
>> +    }
>> +
>> +    t0 = tcg_temp_local_new();
>> +    t1 = tcg_temp_local_new();
>> +    l1 = gen_new_label();
>> +    l2 = gen_new_label();
>> +
>> +    gen_load_gpr(t0, rs);
>> +    gen_load_gpr(t1, rt);
>> +
>> +    if (!is_double) {
>> +        tcg_gen_ext32u_tl(t0, t0);
>> +        tcg_gen_ext32u_tl(t1, t1);
>> +    }
>> +    tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
>> +    tcg_gen_movi_tl(cpu_gpr[rd], 0);
>> +
>> +    tcg_gen_br(l2);
>> +    gen_set_label(l1);
>> +    tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
>> +    tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
> 
> this extend should be conditional on !is_double.

Oops, thanks!

> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> r~
>
diff mbox series

Patch

diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index b56a93a1999..0d5a72064d2 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -14,4 +14,6 @@ 
 @rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &muldiv
 
 DIV.G           011111 ..... ..... ..... 00000 011010   @rs_rt_rd
+DIVU.G          011111 ..... ..... ..... 00000 011011   @rs_rt_rd
 DDIV.G          011111 ..... ..... ..... 00000 011110   @rs_rt_rd
+DDIVU.G         011111 ..... ..... ..... 00000 011111   @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index 331c2226ae3..2e98262b81d 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -16,3 +16,5 @@ 
 
 DIV.G           011100 ..... ..... ..... 00000 010100   @rs_rt_rd
 DDIV.G          011100 ..... ..... ..... 00000 010101   @rs_rt_rd
+DIVU.G          011100 ..... ..... ..... 00000 010110   @rs_rt_rd
+DDIVU.G         011100 ..... ..... ..... 00000 010111   @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index 634d4ba8031..7b3304ec749 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -92,6 +92,61 @@  static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
     return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
 }
 
+static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
+                            bool is_double)
+{
+    TCGv t0, t1;
+    TCGLabel *l1, *l2;
+
+    if (is_double) {
+        if (TARGET_LONG_BITS != 64) {
+            return false;
+        }
+        check_mips_64(s);
+    }
+
+    if (rd == 0) {
+        /* Treat as NOP. */
+        return true;
+    }
+
+    t0 = tcg_temp_local_new();
+    t1 = tcg_temp_local_new();
+    l1 = gen_new_label();
+    l2 = gen_new_label();
+
+    gen_load_gpr(t0, rs);
+    gen_load_gpr(t1, rt);
+
+    if (!is_double) {
+        tcg_gen_ext32u_tl(t0, t0);
+        tcg_gen_ext32u_tl(t1, t1);
+    }
+    tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+    tcg_gen_movi_tl(cpu_gpr[rd], 0);
+
+    tcg_gen_br(l2);
+    gen_set_label(l1);
+    tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
+    tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+    gen_set_label(l2);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a)
+{
+    return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
+{
+    return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
+}
+
 bool decode_loongson(DisasContext *ctx, uint32_t insn)
 {
     if ((ctx->insn_flags & INSN_LOONGSON2E)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7cefff44d74..69463e3b42d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -342,8 +342,6 @@  enum {
     OPC_DMULT_G_2F  = 0x11 | OPC_SPECIAL2,
     OPC_MULTU_G_2F  = 0x12 | OPC_SPECIAL2,
     OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
-    OPC_DIVU_G_2F   = 0x16 | OPC_SPECIAL2,
-    OPC_DDIVU_G_2F  = 0x17 | OPC_SPECIAL2,
     OPC_MOD_G_2F    = 0x1c | OPC_SPECIAL2,
     OPC_DMOD_G_2F   = 0x1d | OPC_SPECIAL2,
     OPC_MODU_G_2F   = 0x1e | OPC_SPECIAL2,
@@ -379,10 +377,8 @@  enum {
     /* Loongson 2E */
     OPC_MULT_G_2E   = 0x18 | OPC_SPECIAL3,
     OPC_MULTU_G_2E  = 0x19 | OPC_SPECIAL3,
-    OPC_DIVU_G_2E   = 0x1B | OPC_SPECIAL3,
     OPC_DMULT_G_2E  = 0x1C | OPC_SPECIAL3,
     OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
-    OPC_DDIVU_G_2E  = 0x1F | OPC_SPECIAL3,
     OPC_MOD_G_2E    = 0x22 | OPC_SPECIAL3,
     OPC_MODU_G_2E   = 0x23 | OPC_SPECIAL3,
     OPC_DMOD_G_2E   = 0x26 | OPC_SPECIAL3,
@@ -5021,22 +5017,6 @@  static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
         tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
         break;
-    case OPC_DIVU_G_2E:
-    case OPC_DIVU_G_2F:
-        {
-            TCGLabel *l1 = gen_new_label();
-            TCGLabel *l2 = gen_new_label();
-            tcg_gen_ext32u_tl(t0, t0);
-            tcg_gen_ext32u_tl(t1, t1);
-            tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
-            tcg_gen_movi_tl(cpu_gpr[rd], 0);
-            tcg_gen_br(l2);
-            gen_set_label(l1);
-            tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
-            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
-            gen_set_label(l2);
-        }
-        break;
     case OPC_MOD_G_2E:
     case OPC_MOD_G_2F:
         {
@@ -5082,19 +5062,6 @@  static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
     case OPC_DMULTU_G_2F:
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
         break;
-    case OPC_DDIVU_G_2E:
-    case OPC_DDIVU_G_2F:
-        {
-            TCGLabel *l1 = gen_new_label();
-            TCGLabel *l2 = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
-            tcg_gen_movi_tl(cpu_gpr[rd], 0);
-            tcg_gen_br(l2);
-            gen_set_label(l1);
-            tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
-            gen_set_label(l2);
-        }
-        break;
     case OPC_DMOD_G_2E:
     case OPC_DMOD_G_2F:
         {
@@ -27100,7 +27067,6 @@  static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MUL:
         gen_arith(ctx, op1, rd, rs, rt);
         break;
-    case OPC_DIVU_G_2F:
     case OPC_MULT_G_2F:
     case OPC_MULTU_G_2F:
     case OPC_MOD_G_2F:
@@ -27134,7 +27100,6 @@  static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_DMULT_G_2F:
     case OPC_DMULTU_G_2F:
-    case OPC_DDIVU_G_2F:
     case OPC_DMOD_G_2F:
     case OPC_DMODU_G_2F:
         check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
@@ -27272,7 +27237,6 @@  static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
 
     op1 = MASK_SPECIAL3(ctx->opcode);
     switch (op1) {
-    case OPC_DIVU_G_2E:
     case OPC_MOD_G_2E:
     case OPC_MODU_G_2E:
     case OPC_MULT_G_2E:
@@ -27542,7 +27506,6 @@  static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
 #if defined(TARGET_MIPS64)
-    case OPC_DDIVU_G_2E:
     case OPC_DMULT_G_2E:
     case OPC_DMULTU_G_2E:
     case OPC_DMOD_G_2E: