| Message ID | 20210113205323.33310-1-yaroshchuk2000@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT | expand |
On Wed, Jan 13, 2021 at 11:53:23PM +0300, yaroshchuk2000@gmail.com wrote: > From: Vladislav Yaroshchuk <yaroshchuk2000@gmail.com> > > Some guests (ex. Darwin-XNU) can attemp to read this MSR to retrieve and > validate CPU topology comparing it to ACPI MADT content > > MSR description from Intel Manual: > 35H: MSR_CORE_THREAD_COUNT: Configured State of Enabled Processor Core > Count and Logical Processor Count > > Bits 15:0 THREAD_COUNT The number of logical processors that are > currently enabled in the physical package > > Bits 31:16 Core_COUNT The number of processor cores that are currently > enabled in the physical package > > Bits 63:32 Reserved > > Signed-off-by: Vladislav Yaroshchuk <yaroshchuk2000@gmail.com> > --- > target/i386/cpu.h | 2 ++ > target/i386/hvf/x86_emu.c | 5 +++++ > 2 files changed, 7 insertions(+) > Queued, thanks! -Roman
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d23a5b340a..cc35676b50 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -371,6 +371,8 @@ typedef enum X86Seg { #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) +#define MSR_CORE_THREAD_COUNT 0x35 + #define MSR_IA32_SYSENTER_CS 0x174 #define MSR_IA32_SYSENTER_ESP 0x175 #define MSR_IA32_SYSENTER_EIP 0x176 diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index da570e352b..2d362763fb 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -668,6 +668,7 @@ void simulate_rdmsr(struct CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -745,6 +746,10 @@ void simulate_rdmsr(struct CPUState *cpu) case MSR_MTRRdefType: val = env->mtrr_deftype; break; + case MSR_CORE_THREAD_COUNT: + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cs->nr_cores << 16u); /* core count, bits 31..16 */ + break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ val = 0;