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Wed, 13 Jan 2021 12:53:32 -0800 (PST) Received: from localhost.localdomain ([188.243.183.134]) by smtp.gmail.com with ESMTPSA id a24sm316167lfi.192.2021.01.13.12.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 12:53:31 -0800 (PST) From: yaroshchuk2000@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH] target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT Date: Wed, 13 Jan 2021 23:53:23 +0300 Message-Id: <20210113205323.33310-1-yaroshchuk2000@gmail.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=yaroshchuk2000@gmail.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 13 Jan 2021 16:18:39 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-trivial@nongnu.org, r.bolshakov@yadro.com, Vladislav Yaroshchuk Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Vladislav Yaroshchuk Some guests (ex. Darwin-XNU) can attemp to read this MSR to retrieve and validate CPU topology comparing it to ACPI MADT content MSR description from Intel Manual: 35H: MSR_CORE_THREAD_COUNT: Configured State of Enabled Processor Core Count and Logical Processor Count Bits 15:0 THREAD_COUNT The number of logical processors that are currently enabled in the physical package Bits 31:16 Core_COUNT The number of processor cores that are currently enabled in the physical package Bits 63:32 Reserved Signed-off-by: Vladislav Yaroshchuk --- target/i386/cpu.h | 2 ++ target/i386/hvf/x86_emu.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d23a5b340a..cc35676b50 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -371,6 +371,8 @@ typedef enum X86Seg { #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) +#define MSR_CORE_THREAD_COUNT 0x35 + #define MSR_IA32_SYSENTER_CS 0x174 #define MSR_IA32_SYSENTER_ESP 0x175 #define MSR_IA32_SYSENTER_EIP 0x176 diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index da570e352b..2d362763fb 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -668,6 +668,7 @@ void simulate_rdmsr(struct CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -745,6 +746,10 @@ void simulate_rdmsr(struct CPUState *cpu) case MSR_MTRRdefType: val = env->mtrr_deftype; break; + case MSR_CORE_THREAD_COUNT: + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cs->nr_cores << 16u); /* core count, bits 31..16 */ + break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ val = 0;