[PULL,v2,31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction

Message ID	20210114162016.2901557-4-f4bug@amsat.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=LYIK=GR=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D62BF23B40 From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: Subject: [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Date: Thu, 14 Jan 2021 17:20:02 +0100 Message-Id: <20210114162016.2901557-4-f4bug@amsat.org> In-Reply-To: <20210114162016.2901557-1-f4bug@amsat.org> References: <20210114162016.2901557-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Aurelien Jarno <aurelien@aurel32.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	None \| expand [PULL,v2,29/69] target/mips/translate: Add declarations for generic code [PULL,v2,30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() [PULL,v2,31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction [PULL,v2,32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h [PULL,v2,35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc() [PULL,v2,36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode [PULL,v2,52/69] target/mips: Introduce decode tree bindings for MSA ASE [PULL,v2,53/69] target/mips: Use decode_ase_msa() generated from decodetree [PULL,v2,54/69] target/mips: Extract LSA/DLSA translation generators [PULL,v2,55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes [PULL,v2,56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes [PULL,v2,57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code [PULL,v2,58/69] target/mips: Convert Rel6 Special2 opcode to decodetree [PULL,v2,63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree [PULL,v2,66/69] target/mips: Remove CPU_R5900 definition [PULL,v2,67/69] target/mips: Remove CPU_NANOMIPS32 definition [PULL,v2,68/69] target/mips: Remove vendor specific CPU definitions

diff --git a/target/mips/translate.h b/target/mips/translate.h index 3d640912f12..98cadffe4e5 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -55,6 +55,7 @@ typedef struct DisasContext { void generate_exception(DisasContext *ctx, int excp); void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 diff --git a/target/mips/translate.c b/target/mips/translate.c index fa11c8ffe0c..d7767215050 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2762,6 +2762,11 @@ void generate_exception_end(DisasContext *ctx, int excp) generate_exception_err(ctx, excp, 0); } +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -2916,7 +2921,7 @@ static inline void check_cp1_enabled(DisasContext *ctx) static inline void check_cop1x(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -2927,7 +2932,7 @@ static inline void check_cop1x(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx) { if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -2945,7 +2950,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) static inline void check_cp1_registers(DisasContext *ctx, int regs) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -2959,7 +2964,7 @@ static inline void check_dsp(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2970,7 +2975,7 @@ static inline void check_dsp_r2(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2981,7 +2986,7 @@ static inline void check_dsp_r3(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2993,7 +2998,7 @@ static inline void check_dsp_r3(DisasContext *ctx) void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3005,7 +3010,7 @@ void check_insn(DisasContext *ctx, uint64_t flags) static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) { if (unlikely(ctx->insn_flags & flags)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3044,7 +3049,7 @@ static inline void check_ps(DisasContext *ctx) void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3065,7 +3070,7 @@ static inline void check_mvh(DisasContext *ctx) static inline void check_xnp(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3077,7 +3082,7 @@ static inline void check_xnp(DisasContext *ctx) static inline void check_pw(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3089,7 +3094,7 @@ static inline void check_pw(DisasContext *ctx) static inline void check_mt(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3106,7 +3111,7 @@ static inline void check_cp0_mt(DisasContext *ctx) generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3119,7 +3124,7 @@ static inline void check_cp0_mt(DisasContext *ctx) static inline void check_nms(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3136,7 +3141,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3147,7 +3152,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) static inline void check_eva(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } @@ -3812,7 +3817,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, break; default: MIPS_INVAL("flt_ldst"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4461,7 +4466,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) break; default: MIPS_INVAL("mfthilo1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4596,7 +4601,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, #endif default: MIPS_INVAL("OPC_PCREL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -4807,7 +4812,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) #endif default: MIPS_INVAL("r6 mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -4865,7 +4870,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) break; default: MIPS_INVAL("div1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5058,7 +5063,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5189,7 +5194,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("mul/madd TXx9"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -5252,7 +5257,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("mul vr54xx"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_store_gpr(t0, rd); @@ -5878,7 +5883,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) break; default: MIPS_INVAL("loongson_cp2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -6067,7 +6072,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, #endif default: MIPS_INVAL("loongson_gsshfl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -6115,13 +6120,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, #endif default: MIPS_INVAL("loongson_gsshfs"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: MIPS_INVAL("loongson_gslsq"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -6170,7 +6175,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, break; default: MIPS_INVAL("loongson_lsdc2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; break; } @@ -6426,7 +6431,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -6489,14 +6494,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute == 0) { @@ -6561,7 +6566,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6632,7 +6637,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6709,14 +6714,14 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute == 0) { @@ -6749,7 +6754,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6772,7 +6777,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6852,7 +6857,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, default: fail: MIPS_INVAL("bitops"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); tcg_temp_free(t1); return; @@ -6930,7 +6935,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) #endif default: MIPS_INVAL("bsfhl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); return; } @@ -10584,7 +10589,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, die: tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, @@ -10794,7 +10799,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, die: tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, @@ -10954,7 +10959,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { gen_helper_deret(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -10977,7 +10982,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, default: die: MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } (void)opn; /* avoid a compiler warning */ @@ -10992,7 +10997,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, TCGv_i32 t0 = tcg_temp_new_i32(); if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -11083,7 +11088,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } ctx->btarget = btarget; @@ -11105,7 +11110,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -11125,7 +11130,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -11433,7 +11438,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) break; default: MIPS_INVAL("cp1 move"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -11570,7 +11575,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_s"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -11607,7 +11612,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_d"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -13041,7 +13046,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, break; default: MIPS_INVAL("farith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13380,7 +13385,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("flt3_arith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13455,13 +13460,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif default: /* Invalid */ MIPS_INVAL("rdhwr"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -13560,7 +13565,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -13622,7 +13627,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -13643,7 +13648,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -13766,7 +13771,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -13940,7 +13945,7 @@ static void gen_mips16_save(DisasContext *ctx, args = 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -14036,7 +14041,7 @@ static void gen_mips16_save(DisasContext *ctx, astatic = 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -14142,7 +14147,7 @@ static void gen_mips16_restore(DisasContext *ctx, astatic = 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -14173,7 +14178,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, int imm, TCGv t0; if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -14231,7 +14236,7 @@ static void decode_i64_mips16(DisasContext *ctx, check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { offset = extended ? offset : offset << 3; gen_ld(ctx, OPC_LDPC, ry, 0, offset); @@ -14308,7 +14313,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14336,7 +14341,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14388,7 +14393,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14451,7 +14456,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -14540,7 +14545,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14568,7 +14573,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14652,7 +14657,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) gen_arith(ctx, OPC_ADDU, ry, reg32, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -14742,7 +14747,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto done; } @@ -14859,7 +14864,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14923,7 +14928,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14938,7 +14943,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -15636,7 +15641,7 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, TCGv_i32 t2; if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -15789,7 +15794,7 @@ static void gen_pool16c_insn(DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -15934,7 +15939,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, TCGv t0, t1; if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -15946,7 +15951,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, switch (opc) { case LWP: if (rd == base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); @@ -15967,7 +15972,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, #ifdef TARGET_MIPS64 case LDP: if (rd == base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ); @@ -16312,7 +16317,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) } else { check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -16362,7 +16367,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) default: pool32axf_invalid: MIPS_INVAL("pool32axf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16631,7 +16636,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) break; default: MIPS_INVAL("pool32fxf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16835,12 +16840,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case SIGRIE: check_insn(ctx, ISA_MIPS_R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: pool32a_invalid: MIPS_INVAL("pool32a"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -16882,7 +16887,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("pool32b"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17362,7 +17367,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) default: pool32f_invalid: MIPS_INVAL("pool32f"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -17524,7 +17529,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) /* Fall through */ default: MIPS_INVAL("pool32i"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17607,7 +17612,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case LD_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c ld-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17646,7 +17651,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case ST_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c st-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17698,7 +17703,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("pool32c"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17990,7 +17995,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -18021,7 +18026,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) case 7: /* LB32, LH32, LWC132, LDC132, LW32 */ if (ctx->hflags & MIPS_HFLAG_BDS16) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18032,7 +18037,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) case 3: /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ if (ctx->hflags & MIPS_HFLAG_BDS32) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18105,7 +18110,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) case POOL16F: check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { /* MOVEP */ int enc_dest = uMIPS_RD(ctx->opcode); @@ -18243,7 +18248,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) case RES_29: case RES_31: case RES_39: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: decode_micromips32_opc(env, ctx); @@ -19501,7 +19506,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case 1: @@ -19516,7 +19521,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; } @@ -19566,7 +19571,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -19607,7 +19612,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -19658,7 +19663,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_helper_shilo(t0, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19732,7 +19737,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -19770,7 +19775,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19793,7 +19798,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19820,7 +19825,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19847,12 +19852,12 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -19996,7 +20001,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, ret); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20089,7 +20094,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -20232,7 +20237,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_bshfl(ctx, OPC_WSBH, ret, rs); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -20287,7 +20292,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -20384,7 +20389,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20395,7 +20400,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -20428,7 +20433,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, case NM_BBNEZC: check_nms(ctx); if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } else if (rt == 0 && opc == NM_BBEQZC) { /* Unconditional branch */ @@ -20478,7 +20483,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Immediate Value Compact branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -20591,7 +20596,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -20603,7 +20608,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -20664,7 +20669,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -20708,7 +20713,7 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } @@ -20838,7 +20843,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -20855,7 +20860,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx) rd = extract32(ctx->opcode, 11, 5); if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } check_cp1_enabled(ctx); @@ -20929,7 +20934,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx) gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21118,7 +21123,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx) gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21135,12 +21140,12 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx) gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21666,7 +21671,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, gen_store_gpr(v1_t, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21688,7 +21693,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21716,13 +21721,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 19, 2)) { case NM_SIGRIE: default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case NM_P_SYSCALL: if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK: @@ -21733,7 +21738,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -21791,12 +21796,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_pool32axf_nanomips_insn(env, ctx); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21815,7 +21820,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21886,7 +21891,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 6; @@ -21921,12 +21926,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; case NM_P_SR_F: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22014,7 +22019,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22027,12 +22032,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22100,7 +22105,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, OPC_SH, rt, 28, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22122,7 +22127,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22182,7 +22187,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22245,7 +22250,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22385,7 +22390,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22405,7 +22410,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) true); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22456,7 +22461,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22500,7 +22505,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22535,7 +22540,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22584,7 +22589,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22600,7 +22605,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 4; @@ -22639,7 +22644,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) if (extract32(ctx->opcode, 2, 1) == 0) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK16: @@ -22650,14 +22655,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22696,7 +22701,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22745,7 +22750,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22781,7 +22786,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) gen_ld(ctx, OPC_LBU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22800,7 +22805,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) gen_ld(ctx, OPC_LHU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23579,7 +23584,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23694,7 +23699,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24385,7 +24390,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK APPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24419,7 +24424,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK DAPPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24688,7 +24693,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24705,7 +24710,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) */ gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case R6_OPC_SDBBP: @@ -24713,7 +24718,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -24734,7 +24739,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_DMULT: @@ -24757,14 +24762,14 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; #endif default: /* Invalid */ MIPS_INVAL("special_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24811,7 +24816,7 @@ static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("special_tx79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24882,16 +24887,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_SPIM: #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("SPIM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else /* Implemented as RI exception for now. */ MIPS_INVAL("spim (unofficial)"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; default: /* Invalid */ MIPS_INVAL("special_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24913,7 +24918,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) rs == 0 && rt == 0) { /* PAUSE */ if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24933,7 +24938,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24959,7 +24964,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24993,7 +24998,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("PMON / selsl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else gen_helper_0e0i(pmon, sa); #endif @@ -25034,7 +25039,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25052,7 +25057,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25084,7 +25089,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25149,7 +25154,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) rd = extract32(opcode, 11, 5); if (unlikely(pd != 0)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else if (rd == 0) { /* nop */ } else if (rt == 0) { @@ -26356,16 +26361,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q8SLT: /* TODO: Implement emulation of Q8SLT instruction. */ MIPS_INVAL("OPC_MXU_Q8SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SLTU: /* TODO: Implement emulation of Q8SLTU instruction. */ MIPS_INVAL("OPC_MXU_Q8SLTU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26395,41 +26400,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32SLT: /* TODO: Implement emulation of S32SLT instruction. */ MIPS_INVAL("OPC_MXU_S32SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16SLT: /* TODO: Implement emulation of D16SLT instruction. */ MIPS_INVAL("OPC_MXU_D16SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVG: /* TODO: Implement emulation of D16AVG instruction. */ MIPS_INVAL("OPC_MXU_D16AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVGR: /* TODO: Implement emulation of D16AVGR instruction. */ MIPS_INVAL("OPC_MXU_D16AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVG: /* TODO: Implement emulation of Q8AVG instruction. */ MIPS_INVAL("OPC_MXU_Q8AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVGR: /* TODO: Implement emulation of Q8AVGR instruction. */ MIPS_INVAL("OPC_MXU_Q8AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ADD: /* TODO: Implement emulation of Q8ADD instruction. */ MIPS_INVAL("OPC_MXU_Q8ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26452,26 +26457,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32CPS: /* TODO: Implement emulation of S32CPS instruction. */ MIPS_INVAL("OPC_MXU_S32CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16CPS: /* TODO: Implement emulation of D16CPS instruction. */ MIPS_INVAL("OPC_MXU_D16CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ABD: /* TODO: Implement emulation of Q8ABD instruction. */ MIPS_INVAL("OPC_MXU_Q8ABD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SAT: /* TODO: Implement emulation of Q16SAT instruction. */ MIPS_INVAL("OPC_MXU_Q16SAT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26501,16 +26506,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D16MULF: /* TODO: Implement emulation of D16MULF instruction. */ MIPS_INVAL("OPC_MXU_D16MULF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MULE: /* TODO: Implement emulation of D16MULE instruction. */ MIPS_INVAL("OPC_MXU_D16MULE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26536,7 +26541,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26559,16 +26564,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32STD: /* TODO: Implement emulation of S32STD instruction. */ MIPS_INVAL("OPC_MXU_S32STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDR: /* TODO: Implement emulation of S32STDR instruction. */ MIPS_INVAL("OPC_MXU_S32STDR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26591,16 +26596,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32LDDV: /* TODO: Implement emulation of S32LDDV instruction. */ MIPS_INVAL("OPC_MXU_S32LDDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDDVR: /* TODO: Implement emulation of S32LDDVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26623,16 +26628,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32STDV: /* TODO: Implement emulation of S32TDV instruction. */ MIPS_INVAL("OPC_MXU_S32TDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDVR: /* TODO: Implement emulation of S32TDVR instruction. */ MIPS_INVAL("OPC_MXU_S32TDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26655,16 +26660,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32LDI: /* TODO: Implement emulation of S32LDI instruction. */ MIPS_INVAL("OPC_MXU_S32LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIR: /* TODO: Implement emulation of S32LDIR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26687,16 +26692,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32SDI: /* TODO: Implement emulation of S32SDI instruction. */ MIPS_INVAL("OPC_MXU_S32SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIR: /* TODO: Implement emulation of S32SDIR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26719,16 +26724,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32LDIV: /* TODO: Implement emulation of S32LDIV instruction. */ MIPS_INVAL("OPC_MXU_S32LDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIVR: /* TODO: Implement emulation of S32LDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26751,16 +26756,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32SDIV: /* TODO: Implement emulation of S32SDIV instruction. */ MIPS_INVAL("OPC_MXU_S32SDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIVR: /* TODO: Implement emulation of S32SDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26783,21 +26788,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D32ACC: /* TODO: Implement emulation of D32ACC instruction. */ MIPS_INVAL("OPC_MXU_D32ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ACCM: /* TODO: Implement emulation of D32ACCM instruction. */ MIPS_INVAL("OPC_MXU_D32ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ASUM: /* TODO: Implement emulation of D32ASUM instruction. */ MIPS_INVAL("OPC_MXU_D32ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26820,21 +26825,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q16ACC: /* TODO: Implement emulation of Q16ACC instruction. */ MIPS_INVAL("OPC_MXU_Q16ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ACCM: /* TODO: Implement emulation of Q16ACCM instruction. */ MIPS_INVAL("OPC_MXU_Q16ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ASUM: /* TODO: Implement emulation of Q16ASUM instruction. */ MIPS_INVAL("OPC_MXU_Q16ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26864,21 +26869,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q8ADDE: /* TODO: Implement emulation of Q8ADDE instruction. */ MIPS_INVAL("OPC_MXU_Q8ADDE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUM: /* TODO: Implement emulation of D8SUM instruction. */ MIPS_INVAL("OPC_MXU_D8SUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUMC: /* TODO: Implement emulation of D8SUMC instruction. */ MIPS_INVAL("OPC_MXU_D8SUMC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26908,26 +26913,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32MUL: /* TODO: Implement emulation of S32MUL instruction. */ MIPS_INVAL("OPC_MXU_S32MUL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MULU: /* TODO: Implement emulation of S32MULU instruction. */ MIPS_INVAL("OPC_MXU_S32MULU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTR: /* TODO: Implement emulation of S32EXTR instruction. */ MIPS_INVAL("OPC_MXU_S32EXTR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTRV: /* TODO: Implement emulation of S32EXTRV instruction. */ MIPS_INVAL("OPC_MXU_S32EXTRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26975,12 +26980,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D32SARW: /* TODO: Implement emulation of D32SARW instruction. */ MIPS_INVAL("OPC_MXU_D32SARW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALN: /* TODO: Implement emulation of S32ALN instruction. */ MIPS_INVAL("OPC_MXU_S32ALN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALNI: gen_mxu_S32ALNI(ctx); @@ -26988,7 +26993,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32LUI: /* TODO: Implement emulation of S32LUI instruction. */ MIPS_INVAL("OPC_MXU_S32LUI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); @@ -27004,7 +27009,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27027,31 +27032,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_LXW: /* TODO: Implement emulation of LXW instruction. */ MIPS_INVAL("OPC_MXU_LXW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXH: /* TODO: Implement emulation of LXH instruction. */ MIPS_INVAL("OPC_MXU_LXH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXHU: /* TODO: Implement emulation of LXHU instruction. */ MIPS_INVAL("OPC_MXU_LXHU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXB: /* TODO: Implement emulation of LXB instruction. */ MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXBU: /* TODO: Implement emulation of LXBU instruction. */ MIPS_INVAL("OPC_MXU_LXBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27073,36 +27078,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D32SLLV: /* TODO: Implement emulation of D32SLLV instruction. */ MIPS_INVAL("OPC_MXU_D32SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLRV: /* TODO: Implement emulation of D32SLRV instruction. */ MIPS_INVAL("OPC_MXU_D32SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARV: /* TODO: Implement emulation of D32SARV instruction. */ MIPS_INVAL("OPC_MXU_D32SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLLV: /* TODO: Implement emulation of Q16SLLV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLRV: /* TODO: Implement emulation of Q16SLRV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SARV: /* TODO: Implement emulation of Q16SARV instruction. */ MIPS_INVAL("OPC_MXU_Q16SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27128,7 +27133,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27151,36 +27156,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q8MOVZ: /* TODO: Implement emulation of Q8MOVZ instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MOVN: /* TODO: Implement emulation of Q8MOVN instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVZ: /* TODO: Implement emulation of D16MOVZ instruction. */ MIPS_INVAL("OPC_MXU_D16MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVN: /* TODO: Implement emulation of D16MOVN instruction. */ MIPS_INVAL("OPC_MXU_D16MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVZ: /* TODO: Implement emulation of S32MOVZ instruction. */ MIPS_INVAL("OPC_MXU_S32MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVN: /* TODO: Implement emulation of S32MOVN instruction. */ MIPS_INVAL("OPC_MXU_S32MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27203,16 +27208,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q8MAC: /* TODO: Implement emulation of Q8MAC instruction. */ MIPS_INVAL("OPC_MXU_Q8MAC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MACSU: /* TODO: Implement emulation of Q8MACSU instruction. */ MIPS_INVAL("OPC_MXU_Q8MACSU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27271,12 +27276,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ MIPS_INVAL("OPC_MXU_S32MADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MADDU: /* TODO: Implement emulation of S32MADDU instruction. */ MIPS_INVAL("OPC_MXU_S32MADDU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); @@ -27284,12 +27289,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32MSUB: /* TODO: Implement emulation of S32MSUB instruction. */ MIPS_INVAL("OPC_MXU_S32MSUB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MSUBU: /* TODO: Implement emulation of S32MSUBU instruction. */ MIPS_INVAL("OPC_MXU_S32MSUBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL01: decode_opc_mxu__pool01(env, ctx); @@ -27309,27 +27314,27 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D16MACF: /* TODO: Implement emulation of D16MACF instruction. */ MIPS_INVAL("OPC_MXU_D16MACF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MADL: /* TODO: Implement emulation of D16MADL instruction. */ MIPS_INVAL("OPC_MXU_D16MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16MAD: /* TODO: Implement emulation of S16MAD instruction. */ MIPS_INVAL("OPC_MXU_S16MAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ADD: /* TODO: Implement emulation of Q16ADD instruction. */ MIPS_INVAL("OPC_MXU_Q16ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MACE: /* TODO: Implement emulation of D16MACE instruction. */ MIPS_INVAL("OPC_MXU_D16MACE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL04: decode_opc_mxu__pool04(env, ctx); @@ -27358,7 +27363,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_D32ADD: /* TODO: Implement emulation of D32ADD instruction. */ MIPS_INVAL("OPC_MXU_D32ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL12: decode_opc_mxu__pool12(env, ctx); @@ -27372,7 +27377,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q8ACCE: /* TODO: Implement emulation of Q8ACCE instruction. */ MIPS_INVAL("OPC_MXU_Q8ACCE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); @@ -27380,17 +27385,17 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S8STD: /* TODO: Implement emulation of S8STD instruction. */ MIPS_INVAL("OPC_MXU_S8STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDI: /* TODO: Implement emulation of S8LDI instruction. */ MIPS_INVAL("OPC_MXU_S8LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8SDI: /* TODO: Implement emulation of S8SDI instruction. */ MIPS_INVAL("OPC_MXU_S8SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL15: decode_opc_mxu__pool15(env, ctx); @@ -27404,52 +27409,52 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S16LDD: /* TODO: Implement emulation of S16LDD instruction. */ MIPS_INVAL("OPC_MXU_S16LDD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16STD: /* TODO: Implement emulation of S16STD instruction. */ MIPS_INVAL("OPC_MXU_S16STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16LDI: /* TODO: Implement emulation of S16LDI instruction. */ MIPS_INVAL("OPC_MXU_S16LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16SDI: /* TODO: Implement emulation of S16SDI instruction. */ MIPS_INVAL("OPC_MXU_S16SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLR: /* TODO: Implement emulation of D32SLR instruction. */ MIPS_INVAL("OPC_MXU_D32SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARL: /* TODO: Implement emulation of D32SARL instruction. */ MIPS_INVAL("OPC_MXU_D32SARL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SAR: /* TODO: Implement emulation of D32SAR instruction. */ MIPS_INVAL("OPC_MXU_D32SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLL: /* TODO: Implement emulation of Q16SLL instruction. */ MIPS_INVAL("OPC_MXU_Q16SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLR: /* TODO: Implement emulation of Q16SLR instruction. */ MIPS_INVAL("OPC_MXU_Q16SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL18: decode_opc_mxu__pool18(env, ctx); @@ -27457,7 +27462,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q16SAR: /* TODO: Implement emulation of Q16SAR instruction. */ MIPS_INVAL("OPC_MXU_Q16SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); @@ -27471,26 +27476,26 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_Q16SCOP: /* TODO: Implement emulation of Q16SCOP instruction. */ MIPS_INVAL("OPC_MXU_Q16SCOP"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MADL: /* TODO: Implement emulation of Q8MADL instruction. */ MIPS_INVAL("OPC_MXU_Q8MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SFL: /* TODO: Implement emulation of S32SFL instruction. */ MIPS_INVAL("OPC_MXU_S32SFL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SAD: /* TODO: Implement emulation of Q8SAD instruction. */ MIPS_INVAL("OPC_MXU_Q8SAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } gen_set_label(l_exit); @@ -27569,7 +27574,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27591,7 +27596,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) case R6_OPC_PREF: if (rt >= 24) { /* hint codes 24-31 are reserved and signal RI */ - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } /* Treat as NOP. */ break; @@ -27630,7 +27635,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) #ifndef CONFIG_USER_ONLY case OPC_GINV: if (unlikely(ctx->gi <= 1)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } check_cp0_enabled(ctx); switch ((ctx->opcode >> 6) & 3) { @@ -27641,7 +27646,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27682,7 +27687,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27733,13 +27738,13 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ADDUH.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else if (ctx->insn_flags & INSN_LOONGSON2E) { gen_loongson_integer(ctx, op1, rd, rs, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_LX_DSP: @@ -27755,7 +27760,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK LX"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27786,7 +27791,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ABSQ_S.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27823,7 +27828,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -27863,7 +27868,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27899,7 +27904,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAW.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27929,7 +27934,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK INSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27964,7 +27969,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28010,7 +28015,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28049,7 +28054,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28094,7 +28099,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28131,7 +28136,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28170,7 +28175,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAQ.W.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28200,7 +28205,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK DINSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28210,7 +28215,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28248,11 +28253,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */ case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */ case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */ break; default: MIPS_INVAL("TX79 MMI class MMI0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28280,11 +28285,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */ case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */ case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */ break; default: MIPS_INVAL("TX79 MMI class MMI1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28315,14 +28320,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */ case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */ case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; case MMI_OPC_2_PCPYLD: gen_mmi_pcpyld(ctx); break; default: MIPS_INVAL("TX79 MMI class MMI2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28343,7 +28348,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; case MMI_OPC_3_PCPYH: gen_mmi_pcpyh(ctx); @@ -28353,7 +28358,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("TX79 MMI class MMI3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28407,23 +28412,23 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */ case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */ case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */ break; default: MIPS_INVAL("TX79 MMI class"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ } static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ } /* @@ -28631,7 +28636,7 @@ static inline int check_msa_access(DisasContext *ctx) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } @@ -28640,7 +28645,7 @@ static inline int check_msa_access(DisasContext *ctx) generate_exception_end(ctx, EXCP_MSADIS); return 0; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } } @@ -28697,7 +28702,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1) check_msa_access(ctx); if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } switch (op1) { @@ -28772,7 +28777,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) { uint8_t df = (ctx->opcode >> 24) & 0x3; if (df == DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { TCGv_i32 tdf = tcg_const_i32(df); gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); @@ -28782,7 +28787,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -28854,7 +28859,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -28890,7 +28895,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) m = dfm & 0x7; df = DF_BYTE; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -28938,7 +28943,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -29783,7 +29788,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_HSUB_S_df: case OPC_HSUB_U_df: if (df == DF_BYTE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } switch (MASK_MSA_3R(ctx->opcode)) { @@ -29921,7 +29926,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free_i32(twd); @@ -29953,7 +29958,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -29990,12 +29995,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df == DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) && (df == DF_WORD)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30065,7 +30070,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); @@ -30095,7 +30100,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx) gen_msa_elm_3e(env, ctx); return; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } @@ -30250,7 +30255,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -30278,7 +30283,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df == DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30334,7 +30339,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -30449,7 +30454,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -30478,7 +30483,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -30576,7 +30581,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } @@ -30660,7 +30665,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } else { gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); @@ -30679,7 +30684,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SIGRIE: check_insn(ctx, ISA_MIPS_R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_SYNCI: check_insn(ctx, ISA_MIPS_R2); @@ -30714,7 +30719,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("regimm"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30823,7 +30828,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("mfmc0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -30840,7 +30845,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30876,7 +30881,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ if (ctx->insn_flags & ISA_MIPS_R6) { if (rt == 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ @@ -30889,7 +30894,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ if (ctx->insn_flags & ISA_MIPS_R6) { if (rt == 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ @@ -31138,7 +31143,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -31224,7 +31229,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -31289,7 +31294,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif @@ -31307,7 +31312,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) tcg_temp_free(t0); } #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); MIPS_INVAL("major opcode"); #endif } else { @@ -31333,7 +31338,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -31438,7 +31443,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); insn_bytes = decode_mips16_opc(env, ctx); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); g_assert(ctx->base.is_jmp == DISAS_NORETURN); return; }

[PULL,v2,31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction

Commit Message

Patch