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17 Jan 2021 13:38:46 -0800 IronPort-SDR: pP5pZnCcj9sSGPgRsIM8sn1Wqw30erkfxWcH+aHoXJddIuY/MoC8pO+ON21VP52RdmgjQHtizI apE1/07tnQ97TX+SfbWCt3DC5OVKehYVqrWkULJW2YbBVwcibVD6oQRSOtYDdPZUo1fJC6TRpk AMkgFmRRR3CDQo+AGB2pedUcJRV+AWUof5EDEpNVvknKWLLUuO3N0k0kiUse3qEnSgLUJC1+Kl DTOlwcUcbMslM4rhDldFbiGcjrk1xdysiGu9Bg1QOXfeO7jLVAnfS+WtATXzXWtLpFxrbFZ7k8 3NM= WDCIronportException: Internal Received: from 7l95g12.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.251]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Jan 2021 13:54:07 -0800 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external Date: Sun, 17 Jan 2021 13:53:59 -0800 Message-Id: <20210117215403.2277103-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117215403.2277103-1-alistair.francis@wdc.com> References: <20210117215403.2277103-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=64494dccb=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng In preparation to generate the CSR register list for GDB stub dynamically, change csr_ops[] to non-static so that it can be referenced externally. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/csr.c | 10 +--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6339e84819..464653d70d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,14 @@ typedef struct { riscv_csr_op_fn op; } riscv_csr_operations; +/* CSR function table constants */ +enum { + CSR_TABLE_SIZE = 0x1000 +}; + +/* CSR function table */ +extern riscv_csr_operations csr_ops[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 10ab82ed1f..507e8ee763 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,14 +23,6 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" -/* CSR function table */ -static riscv_csr_operations csr_ops[]; - -/* CSR function table constants */ -enum { - CSR_TABLE_SIZE = 0x1000 -}; - /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -1378,7 +1370,7 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, } /* Control and Status Register function table */ -static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { +riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* User Floating-Point CSRs */ [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, [CSR_FRM] = { fs, read_frm, write_frm },