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[RFC,v1,3/3] hw: ssi: xilinx_spi: Change to use ssi_txfifo_transfer

Message ID 20210119130155.30194-4-frasse.iglesias@gmail.com (mailing list archive)
State New, archived
Headers show
Series Introduce ssi_txfifo_transfer | expand

Commit Message

Francisco Iglesias Jan. 19, 2021, 1:01 p.m. UTC
This patch changes the SPI controller to use the ssi_txfifo_transfer for
being able to support SPI flash commands requiring dummy clock cycles.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
---
 hw/ssi/xilinx_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index 49ff275593..ae34cdc436 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -179,7 +179,7 @@  static void spi_flush_txfifo(XilinxSPI *s)
     while (!fifo8_is_empty(&s->tx_fifo)) {
         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
         DB_PRINT("data tx:%x\n", tx);
-        rx = ssi_transfer(s->spi, tx);
+        rx = ssi_txfifo_transfer(s->spi, tx);
         DB_PRINT("data rx:%x\n", rx);
         if (fifo8_is_full(&s->rx_fifo)) {
             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;