mbox

[PULL,00/33] target-arm queue

Message ID 20210119151104.16264-1-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show

Pull-request

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119

Message

Peter Maydell Jan. 19, 2021, 3:10 p.m. UTC
Arm pullreq: Rémi's ARMv8.4-SEL2 support is the big thing here.

thanks
-- PMM

The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:

  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119

for you to fetch changes up to 6d39956891b3d1857af84f72f0230a6d99eb3b6a:

  docs: Build and install all the docs in a single manual (2021-01-19 14:38:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement IMPDEF pauth algorithm
 * Support ARMv8.4-SEL2
 * Fix bug where we were truncating predicate vector lengths in SVE insns
 * Implement new pvpanic-pci device
 * npcm7xx_adc-test: Fix memleak in adc_qom_set
 * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Gan Qixin (1):
      npcm7xx_adc-test: Fix memleak in adc_qom_set

Mihai Carabas (4):
      hw/misc/pvpanic: split-out generic and bus dependent code
      hw/misc/pvpanic: add PCI interface support
      pvpanic : update pvpanic spec document
      tests/qtest: add a test case for pvpanic-pci

Peter Maydell (1):
      docs: Build and install all the docs in a single manual

Philippe Mathieu-Daudé (1):
      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error

Richard Henderson (7):
      target/arm: Implement an IMPDEF pauth algorithm
      target/arm: Add cpu properties to control pauth
      target/arm: Use object_property_add_bool for "sve" property
      target/arm: Introduce PREDDESC field definitions
      target/arm: Update PFIRST, PNEXT for pred_desc
      target/arm: Update ZIP, UZP, TRN for pred_desc
      target/arm: Update REV, PUNPK for pred_desc

Rémi Denis-Courmont (19):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: Define isar_feature function to test for presence of SEL2
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: handle VMID change in secure state
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: translate NS bit in page-walks
      target/arm: generalize 2-stage page-walk condition
      target/arm: secure stage 2 translation regime
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: revector to run-time pick target EL
      target/arm: Implement SCR_EL2.EEL2
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()

 docs/conf.py                     |  46 ++++-
 docs/devel/conf.py               |  15 --
 docs/index.html.in               |  17 --
 docs/interop/conf.py             |  28 ---
 docs/meson.build                 |  64 +++---
 docs/specs/conf.py               |  16 --
 docs/specs/pci-ids.txt           |   1 +
 docs/specs/pvpanic.txt           |  13 +-
 docs/system/arm/cpu-features.rst |  21 ++
 docs/system/conf.py              |  28 ---
 docs/tools/conf.py               |  37 ----
 docs/user/conf.py                |  15 --
 include/hw/misc/pvpanic.h        |  24 ++-
 include/hw/pci/pci.h             |   1 +
 include/qemu/xxhash.h            |  98 +++++++++
 target/arm/cpu-param.h           |   2 +-
 target/arm/cpu.h                 | 107 ++++++++--
 target/arm/internals.h           |  45 +++++
 hw/misc/pvpanic-isa.c            |  94 +++++++++
 hw/misc/pvpanic-pci.c            |  95 +++++++++
 hw/misc/pvpanic.c                |  85 +-------
 target/arm/cpu.c                 |  23 ++-
 target/arm/cpu64.c               |  65 ++++--
 target/arm/helper-a64.c          |   8 +-
 target/arm/helper.c              | 414 ++++++++++++++++++++++++++-------------
 target/arm/m_helper.c            |   2 +-
 target/arm/monitor.c             |   1 +
 target/arm/op_helper.c           |   4 +-
 target/arm/pauth_helper.c        |  27 ++-
 target/arm/sve_helper.c          |  33 ++--
 target/arm/tlb_helper.c          |   3 +
 target/arm/translate-a64.c       |   4 +
 target/arm/translate-sve.c       |  31 ++-
 target/arm/translate.c           |  36 +++-
 tests/qtest/arm-cpu-features.c   |  13 ++
 tests/qtest/npcm7xx_adc-test.c   |   1 +
 tests/qtest/pvpanic-pci-test.c   |  62 ++++++
 .gitlab-ci.yml                   |   4 +-
 hw/i386/Kconfig                  |   2 +-
 hw/misc/Kconfig                  |  12 +-
 hw/misc/meson.build              |   4 +-
 tests/qtest/meson.build          |   3 +-
 42 files changed, 1080 insertions(+), 524 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/misc/pvpanic-isa.c
 create mode 100644 hw/misc/pvpanic-pci.c
 create mode 100644 tests/qtest/pvpanic-pci-test.c

Comments

no-reply@patchew.org Jan. 19, 2021, 4 p.m. UTC | #1
Patchew URL: https://patchew.org/QEMU/20210119151104.16264-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210119151104.16264-1-peter.maydell@linaro.org
Subject: [PULL 00/33] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   c114af1..f1fcb68  master     -> master
 - [tag update]      patchew/20210115210456.1053477-1-richard.henderson@linaro.org -> patchew/20210115210456.1053477-1-richard.henderson@linaro.org
 - [tag update]      patchew/20210118123448.307825-1-kwolf@redhat.com -> patchew/20210118123448.307825-1-kwolf@redhat.com
 - [tag update]      patchew/20210118163113.780171-1-pbonzini@redhat.com -> patchew/20210118163113.780171-1-pbonzini@redhat.com
 - [tag update]      patchew/20210119144032.305380-1-pbonzini@redhat.com -> patchew/20210119144032.305380-1-pbonzini@redhat.com
 * [new tag]         patchew/20210119151104.16264-1-peter.maydell@linaro.org -> patchew/20210119151104.16264-1-peter.maydell@linaro.org
Switched to a new branch 'test'
aa63d81 docs: Build and install all the docs in a single manual
ff9c40d target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
754cc2b npcm7xx_adc-test: Fix memleak in adc_qom_set
7cd67a0 tests/qtest: add a test case for pvpanic-pci
1661241 pvpanic : update pvpanic spec document
9dadc4f hw/misc/pvpanic: add PCI interface support
6f421bc hw/misc/pvpanic: split-out generic and bus dependent code
c0b7cac target/arm: Update REV, PUNPK for pred_desc
6573b29 target/arm: Update ZIP, UZP, TRN for pred_desc
f4338e1 target/arm: Update PFIRST, PNEXT for pred_desc
34fbd9e target/arm: Introduce PREDDESC field definitions
33a243c target/arm: refactor vae1_tlbmask()
37bbe6b target/arm: enable Secure EL2 in max CPU
9074a0d target/arm: Implement SCR_EL2.EEL2
f5a272b target/arm: revector to run-time pick target EL
ca06afd target/arm: set HPFAR_EL2.NS on secure stage 2 faults
e81a239 target/arm: secure stage 2 translation regime
8063974 target/arm: generalize 2-stage page-walk condition
c2fb95e target/arm: translate NS bit in page-walks
21980ca target/arm: do S1_ptw_translate() before address space lookup
fc3932f target/arm: handle VMID change in secure state
7690e7c target/arm: add ARMv8.4-SEL2 system registers
cb61b29 target/arm: add MMU stage 1 for Secure EL2
6968841 target/arm: add 64-bit S-EL2 to EL exception table
733a019 target/arm: Define isar_feature function to test for presence of SEL2
4e60cf8 target/arm: factor MDCR_EL2 common handling
b5c5cb6 target/arm: use arm_hcr_el2_eff() where applicable
8462601 target/arm: use arm_is_el2_enabled() where applicable
cfd1d61 target/arm: add arm_is_el2_enabled() helper
b2d2a82 target/arm: remove redundant tests
1f43e13 target/arm: Use object_property_add_bool for "sve" property
f6c437b target/arm: Add cpu properties to control pauth
fd151e4 target/arm: Implement an IMPDEF pauth algorithm

=== OUTPUT BEGIN ===
1/33 Checking commit fd151e40ad26 (target/arm: Implement an IMPDEF pauth algorithm)
2/33 Checking commit f6c437b89b8a (target/arm: Add cpu properties to control pauth)
3/33 Checking commit 1f43e13a98da (target/arm: Use object_property_add_bool for "sve" property)
4/33 Checking commit b2d2a82f259e (target/arm: remove redundant tests)
5/33 Checking commit cfd1d619303f (target/arm: add arm_is_el2_enabled() helper)
6/33 Checking commit 846260135460 (target/arm: use arm_is_el2_enabled() where applicable)
7/33 Checking commit b5c5cb67f89e (target/arm: use arm_hcr_el2_eff() where applicable)
8/33 Checking commit 4e60cf8eff3d (target/arm: factor MDCR_EL2 common handling)
9/33 Checking commit 733a019d02cf (target/arm: Define isar_feature function to test for presence of SEL2)
10/33 Checking commit 696884163395 (target/arm: add 64-bit S-EL2 to EL exception table)
WARNING: Block comments use a leading /* on a separate line
#37: FILE: target/arm/helper.c:9005:
+       {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 2,  2, -1,  1 },},},

WARNING: Block comments use a leading /* on a separate line
#38: FILE: target/arm/helper.c:9006:
+      {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1,  1,  1 },},

WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/arm/helper.c:9007:
+       {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 2,  2,  2,  1 },},},},

WARNING: Block comments use a leading /* on a separate line
#44: FILE: target/arm/helper.c:9010:
+      {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},

WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/arm/helper.c:9011:
+       {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},},},},

WARNING: Block comments use a leading /* on a separate line
#58: FILE: target/arm/op_helper.c:655:
+        /* Requesting a trap to EL2 when we're in EL3 is

total: 0 errors, 6 warnings, 30 lines checked

Patch 10/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/33 Checking commit cb61b29082ea (target/arm: add MMU stage 1 for Secure EL2)
12/33 Checking commit 7690e7c1a05c (target/arm: add ARMv8.4-SEL2 system registers)
13/33 Checking commit fc3932f4b7eb (target/arm: handle VMID change in secure state)
14/33 Checking commit 21980cabcb9b (target/arm: do S1_ptw_translate() before address space lookup)
15/33 Checking commit c2fb95e435d0 (target/arm: translate NS bit in page-walks)
16/33 Checking commit 8063974dff0f (target/arm: generalize 2-stage page-walk condition)
17/33 Checking commit e81a2390c582 (target/arm: secure stage 2 translation regime)
18/33 Checking commit ca06afdd1568 (target/arm: set HPFAR_EL2.NS on secure stage 2 faults)
19/33 Checking commit f5a272bd3d4b (target/arm: revector to run-time pick target EL)
20/33 Checking commit 9074a0dec112 (target/arm: Implement SCR_EL2.EEL2)
WARNING: Block comments use a leading /* on a separate line
#92: FILE: target/arm/helper.c:3397:
+        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in

total: 0 errors, 1 warnings, 110 lines checked

Patch 20/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/33 Checking commit 37bbe6b83f65 (target/arm: enable Secure EL2 in max CPU)
22/33 Checking commit 33a243cd07a3 (target/arm: refactor vae1_tlbmask())
23/33 Checking commit 34fbd9e41fcd (target/arm: Introduce PREDDESC field definitions)
24/33 Checking commit f4338e141e6f (target/arm: Update PFIRST, PNEXT for pred_desc)
25/33 Checking commit 6573b2952a1c (target/arm: Update ZIP, UZP, TRN for pred_desc)
26/33 Checking commit c0b7cac1472c (target/arm: Update REV, PUNPK for pred_desc)
27/33 Checking commit 6f421bc572ca (hw/misc/pvpanic: split-out generic and bus dependent code)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#87: 
new file mode 100644

ERROR: line over 90 characters
#159: FILE: hw/misc/pvpanic-isa.c:68:
+    DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),

WARNING: line over 80 characters
#255: FILE: hw/misc/pvpanic.c:69:
+    memory_region_init_io(&s->mr, OBJECT(dev), &pvpanic_ops, s, "pvpanic", size);

total: 1 errors, 2 warnings, 238 lines checked

Patch 27/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

28/33 Checking commit 9dadc4f92098 (hw/misc/pvpanic: add PCI interface support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
new file mode 100644

total: 0 errors, 1 warnings, 135 lines checked

Patch 28/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/33 Checking commit 1661241c2357 (pvpanic : update pvpanic spec document)
30/33 Checking commit 7cd67a0a9d90 (tests/qtest: add a test case for pvpanic-pci)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

total: 0 errors, 1 warnings, 69 lines checked

Patch 30/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/33 Checking commit 754cc2b92505 (npcm7xx_adc-test: Fix memleak in adc_qom_set)
32/33 Checking commit ff9c40da1e28 (target/arm/m_helper: Silence GCC 10 maybe-uninitialized error)
33/33 Checking commit aa63d810085e (docs: Build and install all the docs in a single manual)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#133: 
deleted file mode 100644

total: 0 errors, 1 warnings, 159 lines checked

Patch 33/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210119151104.16264-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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