target/arm: Conditionalize DBGDIDR

Commit Message

Richard Henderson Jan. 20, 2021, 3:16 a.m. UTC

Only define the register if it exists for the cpu.

Signed-off-by: Richard Henderson <[e-mail]>
---

I've pulled this out of a largely defunct 2019 branch.  This will
be required for the cortex-a76, which only implements aa32 at el0.

This did get some review, back in the day,
https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg05171.html

but it has changed enough that I didn't include the proffered r-b.


r~
---
 target/arm/helper.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

Comments

Peter Maydell Jan. 21, 2021, 7:17 p.m. UTC | #1

On Wed, 20 Jan 2021 at 03:17, Richard Henderson
<[e-mail]> wrote:
>
> Only define the register if it exists for the cpu.
>
> Signed-off-by: Richard Henderson <[e-mail]>
> ---
>
> I've pulled this out of a largely defunct 2019 branch.  This will
> be required for the cortex-a76, which only implements aa32 at el0.
>
> This did get some review, back in the day,
> https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg05171.html
>
> but it has changed enough that I didn't include the proffered r-b.
>



Applied to target-arm.next, thanks.

-- PMM

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbd..10102aab3c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6567,11 +6567,21 @@  static void define_debug_regs(ARMCPU *cpu)
      */
     int i;
     int wrps, brps, ctx_cmps;
-    ARMCPRegInfo dbgdidr = {
-        .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
-        .access = PL0_R, .accessfn = access_tda,
-        .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
-    };
+
+    /*
+     * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
+     * use AArch32.  Given that bit 15 is RES1, if the value is 0 then
+     * the register must not exist for this cpu.
+     */
+    if (cpu->isar.dbgdidr != 0) {
+        ARMCPRegInfo dbgdidr = {
+            .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
+            .opc1 = 0, .opc2 = 0,
+            .access = PL0_R, .accessfn = access_tda,
+            .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
+        };
+        define_one_arm_cp_reg(cpu, &dbgdidr);
+    }
 
     /* Note that all these register fields hold "number of Xs minus 1". */
     brps = arm_num_brps(cpu);
@@ -6580,7 +6590,6 @@  static void define_debug_regs(ARMCPU *cpu)
 
     assert(ctx_cmps <= brps);
 
-    define_one_arm_cp_reg(cpu, &dbgdidr);
     define_arm_cp_regs(cpu, debug_cp_reginfo);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {