diff mbox series

[v2,3/3] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU

Message ID 20210122044537.1823-4-rebecca@nuviainc.com (mailing list archive)
State New, archived
Headers show
Series target/arm: Add support for FEAT_DIT, Data Independent Timing | expand

Commit Message

Rebecca Cran Jan. 22, 2021, 4:45 a.m. UTC
Enable FEAT_DIT for the "max" AARCH64 CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Richard Henderson Jan. 22, 2021, 9:06 p.m. UTC | #1
On 1/21/21 6:45 PM, Rebecca Cran wrote:
> Enable FEAT_DIT for the "max" AARCH64 CPU.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu64.c | 5 +++++
>  1 file changed, 5 insertions(+)

There is also a 32-bit "max" cpu in cpu.c.


r~
Rebecca Cran Jan. 23, 2021, 12:27 a.m. UTC | #2
On 1/22/21 2:06 PM, Richard Henderson wrote:
> On 1/21/21 6:45 PM, Rebecca Cran wrote:
>> Enable FEAT_DIT for the "max" AARCH64 CPU.
>>
>> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/arm/cpu64.c | 5 +++++
>>   1 file changed, 5 insertions(+)
> 
> There is also a 32-bit "max" cpu in cpu.c.

Thanks. I've fixed it in the next revision.
diff mbox series

Patch

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -666,6 +666,7 @@  static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
         t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
+        t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
         cpu->isar.id_aa64pfr0 = t;
 
         t = cpu->isar.id_aa64pfr1;
@@ -715,6 +716,10 @@  static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
         cpu->isar.id_isar6 = u;
 
+        u = cpu->isar.id_pfr0;
+        u = FIELD_DP32(u, ID_PFR0, DIT, 1);
+        cpu->isar.id_pfr0 = u;
+
         u = cpu->isar.id_mmfr3;
         u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
         cpu->isar.id_mmfr3 = u;