@@ -32,7 +32,7 @@ typedef struct AccelCPUClass {
void (*cpu_class_init)(CPUClass *cc);
void (*cpu_instance_init)(CPUState *cpu);
- void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+ bool (*cpu_realizefn)(CPUState *cpu, Error **errp);
} AccelCPUClass;
#endif /* ACCEL_CPU_H */
@@ -89,6 +89,6 @@ void accel_cpu_instance_init(CPUState *cpu);
* @cpu: The CPU that needs to call accel-specific cpu realization.
* @errp: currently unused.
*/
-void accel_cpu_realizefn(CPUState *cpu, Error **errp);
+bool accel_cpu_realizefn(CPUState *cpu, Error **errp);
#endif /* QEMU_ACCEL_H */
@@ -12,7 +12,7 @@
void host_cpu_instance_init(X86CPU *cpu);
void host_cpu_max_instance_init(X86CPU *cpu);
-void host_cpu_realizefn(CPUState *cs, Error **errp);
+bool host_cpu_realizefn(CPUState *cs, Error **errp);
void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);
@@ -98,14 +98,14 @@ void accel_cpu_instance_init(CPUState *cpu)
}
}
-void accel_cpu_realizefn(CPUState *cpu, Error **errp)
+bool accel_cpu_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) {
- /* NB: errp parameter is unused currently */
- cc->accel_cpu->cpu_realizefn(cpu, errp);
+ return cc->accel_cpu->cpu_realizefn(cpu, errp);
}
+ return true;
}
static const TypeInfo accel_cpu_type = {
@@ -130,8 +130,9 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_list_add(cpu);
- accel_cpu_realizefn(cpu, errp);
-
+ if (!accel_cpu_realizefn(cpu, errp)) {
+ return;
+ }
#ifdef CONFIG_TCG
/* NB: errp parameter is unused currently */
if (tcg_enabled()) {
@@ -80,7 +80,7 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu)
return phys_bits;
}
-void host_cpu_realizefn(CPUState *cs, Error **errp)
+bool host_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -97,10 +97,11 @@ void host_cpu_realizefn(CPUState *cs, Error **errp)
error_setg(errp, "phys-bits should be between 32 and %u "
" (but is %u)",
TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
- return;
+ return false;
}
cpu->phys_bits = phys_bits;
}
+ return true;
}
#define CPUID_MODEL_ID_SZ 48
@@ -18,7 +18,7 @@
#include "kvm_i386.h"
#include "hw/core/accel-cpu.h"
-static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
+static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -41,7 +41,7 @@ static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
MSR_IA32_UCODE_REV);
}
}
- host_cpu_realizefn(cs, errp);
+ return host_cpu_realizefn(cs, errp);
}
/*
@@ -96,7 +96,7 @@ static void x86_cpu_machine_done(Notifier *n, void *unused)
}
}
-static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
@@ -132,12 +132,14 @@ static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
/* ... SMRAM with higher priority, linked from /machine/smram. */
cpu->machine_done.notify = x86_cpu_machine_done;
qemu_add_machine_init_done_notifier(&cpu->machine_done);
+ return true;
}
#else /* CONFIG_USER_ONLY */
-static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{
+ return true;
}
#endif /* !CONFIG_USER_ONLY */