diff mbox series

[31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions

Message ID 20210212150256.885-32-zhiwei_liu@c-sky.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: support packed extension v0.9.2 | expand

Commit Message

LIU Zhiwei Feb. 12, 2021, 3:02 p.m. UTC
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/helper.h                   |  6 +++
 target/riscv/insn32-64.decode           |  6 +++
 target/riscv/insn_trans/trans_rvp.c.inc |  7 ++++
 target/riscv/packed_helper.c            | 55 +++++++++++++++++++++++++
 4 files changed, 74 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 673bc4f628..384b42ce90 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1434,4 +1434,10 @@  DEF_HELPER_3(sll32, tl, env, tl, tl)
 DEF_HELPER_3(ksll32, tl, env, tl, tl)
 DEF_HELPER_3(kslra32, tl, env, tl, tl)
 DEF_HELPER_3(kslra32_u, tl, env, tl, tl)
+
+DEF_HELPER_3(smin32, tl, env, tl, tl)
+DEF_HELPER_3(umin32, tl, env, tl, tl)
+DEF_HELPER_3(smax32, tl, env, tl, tl)
+DEF_HELPER_3(umax32, tl, env, tl, tl)
+DEF_HELPER_2(kabs32, tl, env, tl)
 #endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6f0f2923ca..a2b8831467 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -129,3 +129,9 @@  ksll32     0110010  ..... ..... 010 ..... 1111111 @r
 kslli32    1000010  ..... ..... 010 ..... 1111111 @sh5
 kslra32    0101011  ..... ..... 010 ..... 1111111 @r
 kslra32_u  0110011  ..... ..... 010 ..... 1111111 @r
+
+smin32     1001000  ..... ..... 010 ..... 1111111 @r
+umin32     1010000  ..... ..... 010 ..... 1111111 @r
+smax32     1001001  ..... ..... 010 ..... 1111111 @r
+umax32     1010001  ..... ..... 010 ..... 1111111 @r
+kabs32     1010110  10010 ..... 000 ..... 1111111 @r2
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index e52f268a57..ce144ee5c0 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1172,4 +1172,11 @@  GEN_RVP_R_OOL(ksll32);
 GEN_RVP_SHIFTI(kslli32, ksll32, NULL);
 GEN_RVP_R_OOL(kslra32);
 GEN_RVP_R_OOL(kslra32_u);
+
+/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */
+GEN_RVP_R_OOL(smin32);
+GEN_RVP_R_OOL(umin32);
+GEN_RVP_R_OOL(smax32);
+GEN_RVP_R_OOL(umax32);
+GEN_RVP_R2_OOL(kabs32);
 #endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index c168c51eff..c8a92f5b7d 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3377,4 +3377,59 @@  static inline void do_kslra32_u(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR(kslra32_u, 1, 4);
+
+/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */
+static inline void do_smin32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    int32_t *d = vd, *a = va, *b = vb;
+
+    d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR(smin32, 1, 4);
+
+static inline void do_umin32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+
+    d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR(umin32, 1, 4);
+
+static inline void do_smax32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    int32_t *d = vd, *a = va, *b = vb;
+
+    d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR(smax32, 1, 4);
+
+static inline void do_umax32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint32_t *d = vd, *a = va, *b = vb;
+
+    d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR(umax32, 1, 4);
+
+static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+    int32_t *d = vd, *a = va;
+
+    if (a[i] == INT32_MIN) {
+        d[i] = INT32_MAX;
+        env->vxsat = 0x1;
+    } else {
+        d[i] = abs(a[i]);
+    }
+}
+
+RVPR2(kabs32, 1, 4);
 #endif