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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 26/44] hw/arm/armsse: Move s32ktimer into data-driven framework Date: Fri, 19 Feb 2021 14:45:59 +0000 Message-Id: <20210219144617.4782-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move the CMSDK timer that uses the S32K slow clock into the data-driven device placement framework. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +-- hw/arm/armsse.c | 31 ++++++++++++------------------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 3f8f3750577..7416c08a802 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -158,8 +158,7 @@ struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTimer timer[2]; - CMSDKAPBTimer s32ktimer; + CMSDKAPBTimer timer[3]; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 6540ffb919b..3270362d599 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -113,6 +113,16 @@ static const ARMSSEDeviceInfo sse200_devices[] = { .ppc_port = 1, .irq = 4, }, + { + .name = "s32ktimer", + .type = TYPE_CMSDK_APB_TIMER, + .index = 2, + .addr = 0x4002f000, + .ppc = 1, + .ppc_port = 0, + .irq = 2, + .slowclk = true, + }, { .name = "dualtimer", .type = TYPE_CMSDK_APB_DUALTIMER, @@ -425,8 +435,6 @@ static void armsse_init(Object *obj) g_free(name); } - object_initialize_child(obj, "s32ktimer", &s->s32ktimer, - TYPE_CMSDK_APB_TIMER); object_initialize_child(obj, "armsse-sysctl", &s->sysctl, TYPE_IOTKIT_SYSCTL); object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, @@ -858,7 +866,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]); - qdev_connect_clock_in(DEVICE(sbd), "pclk", s->mainclk); + qdev_connect_clock_in(DEVICE(sbd), "pclk", + devinfo->slowclk ? s->s32kclk : s->mainclk); if (!sysbus_realize(sbd, errp)) { return; } @@ -1059,25 +1068,9 @@ static void armsse_realize(DeviceState *dev, Error **errp) } } - /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ - /* Devices behind APB PPC1: - * 0x4002f000: S32K timer - */ - qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, - armsse_get_common_irq_in(s, 2)); - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); - object_property_set_link(OBJECT(&s->apb_ppc[1]), "port[0]", OBJECT(mr), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; } - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc[1]), 0); - memory_region_add_subregion(&s->container, 0x4002f000, mr); dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]); qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0,