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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 39/44] hw/misc/mps2-scc: Implement changes for AN547 Date: Fri, 19 Feb 2021 14:46:12 +0000 Message-Id: <20210219144617.4782-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Implement the minor changes required to the SCC block for AN547 images: * CFG2 and CFG5 exist (like AN524) * CFG3 is reserved (like AN524) * CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this in the TODO comment Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/misc/mps2-scc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 140a4b9ceba..c56aca86ad5 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -110,14 +110,14 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) r = s->cfg1; break; case A_CFG2: - if (scc_partno(s) != 0x524) { + if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { /* CFG2 reserved on other boards */ goto bad_offset; } r = s->cfg2; break; case A_CFG3: - if (scc_partno(s) == 0x524) { + if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) { /* CFG3 reserved on AN524 */ goto bad_offset; } @@ -130,7 +130,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) r = s->cfg4; break; case A_CFG5: - if (scc_partno(s) != 0x524) { + if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { /* CFG5 reserved on other boards */ goto bad_offset; } @@ -185,7 +185,10 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case A_CFG0: - /* TODO on some boards bit 0 controls RAM remapping */ + /* + * TODO on some boards bit 0 controls RAM remapping; + * on others bit 1 is CPU_WAIT. + */ s->cfg0 = value; break; case A_CFG1: @@ -195,7 +198,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, } break; case A_CFG2: - if (scc_partno(s) != 0x524) { + if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { /* CFG2 reserved on other boards */ goto bad_offset; } @@ -203,7 +206,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, s->cfg2 = value; break; case A_CFG5: - if (scc_partno(s) != 0x524) { + if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { /* CFG5 reserved on other boards */ goto bad_offset; }