| Message ID | 20210222130514.2167-6-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI | expand |
On Mon, Feb 22, 2021 at 09:05:14PM +0800, Bin Meng wrote: > From: Xuzhou Cheng <xuzhou.cheng@windriver.com> > > Now that the Xilinx CSU DMA model is implemented, the existing > DMA related dead codes in the ZynqMP QSPI are useless and should > be removed. The maximum register number is also updated to only > include the QSPI registers. > > Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > --- > > Changes in v4: > - Modify XLNX_ZYNQMP_SPIPS_R_MAX > > Changes in v3: > - new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips > > include/hw/ssi/xilinx_spips.h | 2 +- > hw/ssi/xilinx_spips.c | 10 ---------- > 2 files changed, 1 insertion(+), 11 deletions(-) > > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h > index 3eae73480e..06bfd18312 100644 > --- a/include/hw/ssi/xilinx_spips.h > +++ b/include/hw/ssi/xilinx_spips.h > @@ -34,7 +34,7 @@ > typedef struct XilinxSPIPS XilinxSPIPS; > > #define XLNX_SPIPS_R_MAX (0x100 / 4) > -#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) > +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) > > /* Bite off 4k chunks at a time */ > #define LQSPI_CACHE_SIZE 1024 > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index 8a0cc22d42..1e9dba2039 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -195,13 +195,6 @@ > #define R_GQSPI_MOD_ID (0x1fc / 4) > #define R_GQSPI_MOD_ID_RESET (0x10a0000) > > -#define R_QSPIDMA_DST_CTRL (0x80c / 4) > -#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) > -#define R_QSPIDMA_DST_I_MASK (0x820 / 4) > -#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) > -#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) > -#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) > - > /* size of TXRX FIFOs */ > #define RXFF_A (128) > #define TXFF_A (128) > @@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) > s->regs[R_GQSPI_GPIO] = 1; > s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; > s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; > - s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; > - s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; > - s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; > s->man_start_com_g = false; > s->gqspi_irqline = 0; > xlnx_zynqmp_qspips_update_ixr(s); > -- > 2.25.1 >
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 3eae73480e..06bfd18312 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -34,7 +34,7 @@ typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) -#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8a0cc22d42..1e9dba2039 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -195,13 +195,6 @@ #define R_GQSPI_MOD_ID (0x1fc / 4) #define R_GQSPI_MOD_ID_RESET (0x10a0000) -#define R_QSPIDMA_DST_CTRL (0x80c / 4) -#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) -#define R_QSPIDMA_DST_I_MASK (0x820 / 4) -#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) -#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) -#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) - /* size of TXRX FIFOs */ #define RXFF_A (128) #define TXFF_A (128) @@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) s->regs[R_GQSPI_GPIO] = 1; s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; - s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; - s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; - s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; s->man_start_com_g = false; s->gqspi_irqline = 0; xlnx_zynqmp_qspips_update_ixr(s);