@@ -264,3 +264,14 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
}
/* #endif TARGET_AARCH64 , see matching comment above */
+
+uint64_t arm_sctlr(CPUARMState *env, int el)
+{
+ /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
+ if (el == 0) {
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
+ el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
+ ? 2 : 1;
+ }
+ return env->cp15.sctlr_el[el];
+}
@@ -1727,17 +1727,6 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-uint64_t arm_sctlr(CPUARMState *env, int el)
-{
- /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
- if (el == 0) {
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
- el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
- ? 2 : 1;
- }
- return env->cp15.sctlr_el[el];
-}
-
/* Returns true if the stage 1 translation regime is using LPAE format page
* tables. Used when raising alignment exceptions, whose FSR changes depending
* on whether the long or short descriptor format is in use. */
this function is used for kvm too, add it to the cpu-common module. Signed-off-by: Claudio Fontana <cfontana@suse.de> --- target/arm/cpu-common.c | 11 +++++++++++ target/arm/tcg/helper.c | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-)