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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h22sm9089008wmb.36.2021.03.03.13.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v4 21/28] target/arm: Refactor some function bodies Date: Wed, 3 Mar 2021 22:47:01 +0100 Message-Id: <20210303214708.1727801-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Cornelia Huck , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Refactor few fonctions body to ease #ifdef'ry review in the next commit. No logical change intented. Signed-off-by: Philippe Mathieu-Daudé --- Patch easier to review using: 'git-diff --color-moved-ws=allow-indentation-change' --- target/arm/debug_helper.c | 72 +++++++++++++++++++-------------------- target/arm/helper.c | 5 ++- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index c01d8524443..980110e1328 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -230,7 +230,6 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) static bool check_breakpoints(ARMCPU *cpu) { CPUARMState *env = &cpu->env; - int n; /* * If breakpoints are disabled globally or we can't take debug @@ -241,7 +240,7 @@ static bool check_breakpoints(ARMCPU *cpu) return false; } - for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { + for (int n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; } @@ -266,47 +265,48 @@ void arm_debug_excp_handler(CPUState *cs) */ ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + uint64_t pc; + bool same_el; CPUWatchpoint *wp_hit = cs->watchpoint_hit; - if (wp_hit) { - if (wp_hit->flags & BP_CPU) { - bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; - bool same_el = arm_debug_target_el(env) == arm_current_el(env); + if (wp_hit && (wp_hit->flags & BP_CPU)) { + bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; + bool same_el = arm_debug_target_el(env) == arm_current_el(env); - cs->watchpoint_hit = NULL; - - env->exception.fsr = arm_debug_exception_fsr(env); - env->exception.vaddress = wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); - } - } else { - uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); - - /* - * (1) GDB breakpoints should be handled first. - * (2) Do not raise a CPU exception if no CPU breakpoint has fired, - * since singlestep is also done by generating a debug internal - * exception. - */ - if (cpu_breakpoint_test(cs, pc, BP_GDB) - || !cpu_breakpoint_test(cs, pc, BP_CPU)) { - return; - } + cs->watchpoint_hit = NULL; env->exception.fsr = arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress = 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), + env->exception.vaddress = wp_hit->hitaddr; + raise_exception(env, EXCP_DATA_ABORT, + syn_watchpoint(same_el, 0, wnr), arm_debug_target_el(env)); + return; } + + pc = is_a64(env) ? env->pc : env->regs[15]; + same_el = (arm_debug_target_el(env) == arm_current_el(env)); + + /* + * (1) GDB breakpoints should be handled first. + * (2) Do not raise a CPU exception if no CPU breakpoint has fired, + * since singlestep is also done by generating a debug internal + * exception. + */ + if (cpu_breakpoint_test(cs, pc, BP_GDB) + || !cpu_breakpoint_test(cs, pc, BP_CPU)) { + return; + } + + env->exception.fsr = arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress = 0; + raise_exception(env, EXCP_PREFETCH_ABORT, + syn_breakpoint(same_el), + arm_debug_target_el(env)); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e1a3b94211..54648c7fbb6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6595,7 +6595,7 @@ static void define_debug_regs(ARMCPU *cpu) * These are just dummy implementations for now. */ int i; - int wrps, brps, ctx_cmps; + int brps, ctx_cmps; /* * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot @@ -6614,7 +6614,6 @@ static void define_debug_regs(ARMCPU *cpu) /* Note that all these register fields hold "number of Xs minus 1". */ brps = arm_num_brps(cpu); - wrps = arm_num_wrps(cpu); ctx_cmps = arm_num_ctx_cmps(cpu); assert(ctx_cmps <= brps); @@ -6644,7 +6643,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, dbgregs); } - for (i = 0; i < wrps; i++) { + for (i = 0; i < arm_num_wrps(cpu); i++) { ARMCPRegInfo dbgregs[] = { { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,