@@ -599,14 +599,12 @@ enum {
HFLAGS_DR = 4, /* MSR_DR */
HFLAGS_IR = 5, /* MSR_IR */
HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
- HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */
HFLAGS_TM = 8, /* computed from MSR_TM */
HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */
HFLAGS_FP = 13, /* MSR_FP */
- HFLAGS_SA = 22, /* MSR_SA */
- HFLAGS_AP = 23, /* MSR_AP */
+ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
};
@@ -95,8 +95,7 @@ void hreg_compute_hflags(CPUPPCState *env)
/* Some bits come straight across from MSR. */
msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
- (1 << MSR_DR) | (1 << MSR_IR) |
- (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP));
+ (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP));
if (ppc_flags & POWERPC_FLAG_HID0_LE) {
/*
@@ -133,8 +132,8 @@ void hreg_compute_hflags(CPUPPCState *env)
if (ppc_flags & POWERPC_FLAG_VRE) {
msr_mask |= 1 << MSR_VR;
}
- if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) {
- hflags |= 1 << HFLAGS_VSX;
+ if (ppc_flags & POWERPC_FLAG_VSX) {
+ msr_mask |= 1 << MSR_VSX;
}
if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
hflags |= 1 << HFLAGS_TM;
Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/ppc/cpu.h | 4 +--- target/ppc/helper_regs.c | 7 +++---- 2 files changed, 4 insertions(+), 7 deletions(-)