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22 Mar 2021 18:41:46 -0700 IronPort-SDR: NWsLZ9d7143VTwAFBXlEWGzt4hWs03OLI17HO0/8A9uWueju8cwbYFcrTNZWXy++d9UlMRVRV4 8qZ2JAl3ZH94kzheMk0PnwjFQ2ETwoZYoh7IuDloS+4//Zv/7vcfapP8cMeI/74qu6W1XUHall 2p8LDZpOt1oU2X6xBj1jC/++riy5HmPo4Brfe8uOfMdQpm51UAkskm4yilCqlmBzDqXhY1BvcI QvLnkyKSGLdsTu32HhWUpvp8BbX2mHRVws1dQ1Uw9gHZfgcj8HdCNvKWC1dGV57TpW1Dv1imiM diA= WDCIronportException: Internal Received: from cn6ntbqq2.ad.shared (HELO alistair-risc6-laptop.hgst.com) ([10.86.49.5]) by uls-op-cesaip01.wdc.com with ESMTP; 22 Mar 2021 18:59:38 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie Date: Mon, 22 Mar 2021 21:57:51 -0400 Message-Id: <20210323015756.3168650-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210323015756.3168650-1-alistair.francis@wdc.com> References: <20210323015756.3168650-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=709ee912d=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Georg Kotheimer Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Georg Kotheimer The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 68 +++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9dba7f736..d2585395bf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -749,30 +749,42 @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) return write_mstatus(env, CSR_MSTATUS, newval); } +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + /* Shift the VS bits to their S bit location in vsie */ + *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; + return 0; +} + static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) { if (riscv_cpu_virt_enabled(env)) { - /* Tell the guest the VS bits, shifted to the S bit locations */ - *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; + read_vsie(env, CSR_VSIE, val); } else { *val = env->mie & env->mideleg; } return 0; } -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval; + /* Shift the S bits to their VS bit location in mie */ + target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | + ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); + return write_mie(env, CSR_MIE, newval); +} +static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +{ if (riscv_cpu_virt_enabled(env)) { - /* Shift the guests S bits to VS */ - newval = (env->mie & ~VS_MODE_INTERRUPTS) | - ((val << 1) & VS_MODE_INTERRUPTS); + write_vsie(env, CSR_VSIE, val); } else { - newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); + target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | + (val & S_MODE_INTERRUPTS); + write_mie(env, CSR_MIE, newval); } - return write_mie(env, CSR_MIE, newval); + return 0; } static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) @@ -853,17 +865,25 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) return 0; } +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + /* Shift the S bits to their VS bit location in mip */ + int ret = rmw_mip(env, 0, ret_value, new_value << 1, + (write_mask << 1) & vsip_writable_mask & env->hideleg); + *ret_value &= VS_MODE_INTERRUPTS; + /* Shift the VS bits to their S bit location in vsip */ + *ret_value >>= 1; + return ret; +} + static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret; if (riscv_cpu_virt_enabled(env)) { - /* Shift the new values to line up with the VS bits */ - ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, - (write_mask & sip_writable_mask) << 1 & env->mideleg); - ret &= vsip_writable_mask; - ret >>= 1; + ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); @@ -1122,26 +1142,6 @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) return 0; } -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) -{ - int ret = rmw_mip(env, 0, ret_value, new_value, - write_mask & env->mideleg & vsip_writable_mask); - return ret; -} - -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) -{ - *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; - return 0; -} - -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) -{ - target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); - return write_mie(env, CSR_MIE, newval); -} - static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->vstvec;