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[PULL,3/3] target/mips: Fix TCG temporary leak in gen_cache_operation()

Message ID 20210413101131.3480173-4-f4bug@amsat.org (mailing list archive)
State New
Headers show
Series [PULL,1/3] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM | expand

Commit Message

Philippe Mathieu-Daudé April 13, 2021, 10:11 a.m. UTC
Fix a TCG temporary leak when translating CACHE opcode.

Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
 target/mips/translate.c | 2 ++
 1 file changed, 2 insertions(+)
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diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3963b..71fa5ec1973 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12804,6 +12804,8 @@  static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
     TCGv t1 = tcg_temp_new();
     gen_base_offset_addr(ctx, t1, base, offset);
     gen_helper_cache(cpu_env, t1, t0);
+    tcg_temp_free(t1);
+    tcg_temp_free_i32(t0);
 #if defined(TARGET_MIPS64)