diff mbox series

[v3,2/3] target/arm: Make sure that commpage's tb->size != 0

Message ID 20210414134112.25620-3-iii@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series accel/tcg: Make sure that tb->size != 0 after translation | expand

Commit Message

Ilya Leoshkevich April 14, 2021, 1:41 p.m. UTC 
tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.

Fix by pretending that commpage translation blocks have at least one
instruction.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
 target/arm/translate.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 62b1c2081b..885f69b044 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9060,6 +9060,7 @@  static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     unsigned int insn;
 
     if (arm_pre_translate_insn(dc)) {
+        dc->base.pc_next += 4;
         return;
     }