| Message ID | 20210417194205.17057-1-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Patchew URL: https://patchew.org/QEMU/20210417194205.17057-1-peter.maydell@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210417194205.17057-1-peter.maydell@linaro.org Subject: [PULL 0/7] queue of proposed rc4 fixes === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20210417194205.17057-1-peter.maydell@linaro.org -> patchew/20210417194205.17057-1-peter.maydell@linaro.org Switched to a new branch 'test' 72e612f accel/tcg: avoid re-translating one-shot instructions 07afad5 target/arm: drop CF_LAST_IO/dc->condjump check 5dc7b9f hw/arm/armsse: Make SSE-300 use Cortex-M55 425d9fe hw/arm/armsse: Give SSE-300 its own Property array ec5047b include/qemu/osdep.h: Move system includes to top 401fa67 osdep: protect qemu/osdep.h with extern "C" 7cf1c2e osdep: include glib-compat.h before other QEMU headers === OUTPUT BEGIN === 1/7 Checking commit 7cf1c2efd765 (osdep: include glib-compat.h before other QEMU headers) 2/7 Checking commit 401fa67e0303 (osdep: protect qemu/osdep.h with extern "C") WARNING: architecture specific defines should be avoided #80: FILE: include/qemu/compiler.h:14: +#ifdef __cplusplus ERROR: storage class should be at the beginning of the declaration #81: FILE: include/qemu/compiler.h:15: +#define QEMU_EXTERN_C extern "C" ERROR: storage class should be at the beginning of the declaration #83: FILE: include/qemu/compiler.h:17: +#define QEMU_EXTERN_C extern WARNING: architecture specific defines should be avoided #106: FILE: include/qemu/osdep.h:121: +#ifdef __cplusplus WARNING: architecture specific defines should be avoided #117: FILE: include/qemu/osdep.h:735: +#ifdef __cplusplus total: 2 errors, 3 warnings, 56 lines checked Patch 2/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/7 Checking commit ec5047b58ffc (include/qemu/osdep.h: Move system includes to top) WARNING: architecture specific defines should be avoided #37: FILE: include/qemu/osdep.h:111: +#if defined(__linux__) && defined(__sparc__) WARNING: architecture specific defines should be avoided #49: FILE: include/qemu/osdep.h:123: +#ifdef __APPLE__ total: 0 errors, 2 warnings, 50 lines checked Patch 3/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 4/7 Checking commit 425d9fe70cce (hw/arm/armsse: Give SSE-300 its own Property array) 5/7 Checking commit 5dc7b9f9db8b (hw/arm/armsse: Make SSE-300 use Cortex-M55) 6/7 Checking commit 07afad503110 (target/arm: drop CF_LAST_IO/dc->condjump check) 7/7 Checking commit 72e612ff09f4 (accel/tcg: avoid re-translating one-shot instructions) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210417194205.17057-1-peter.maydell@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
On 4/17/21 9:41 PM, Peter Maydell wrote: > This pullreq contains fixes for the remaining "not fixed yet" issues > in the 6.0 Planning page: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > None of these are 100% rc4-worthy on their own, but taken all together > I think they justify rolling another release candidate. I wonder about this one for https://bugs.launchpad.net/qemu/+bug/1914236 "mptsas: remove unused MPTSASState.pending (CVE-2021-3392)" https://www.mail-archive.com/qemu-devel@nongnu.org/msg799236.html which is a respin of https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg02660.html with Paolo's comment addressed. > ---------------------------------------------------------------- > Fixes for rc4: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > ---------------------------------------------------------------- > Alex Bennée (2): > target/arm: drop CF_LAST_IO/dc->condjump check > accel/tcg: avoid re-translating one-shot instructions > > Paolo Bonzini (2): > osdep: include glib-compat.h before other QEMU headers > osdep: protect qemu/osdep.h with extern "C" > > Peter Maydell (3): > include/qemu/osdep.h: Move system includes to top > hw/arm/armsse: Give SSE-300 its own Property array > hw/arm/armsse: Make SSE-300 use Cortex-M55 > > include/qemu/compiler.h | 6 ++++++ > include/qemu/osdep.h | 38 +++++++++++++++++++++++++++++--------- > accel/tcg/translate-all.c | 2 +- > hw/arm/armsse.c | 24 +++++++++++++++++++----- > target/arm/translate.c | 5 ----- > disas/arm-a64.cc | 2 +- > disas/nanomips.cpp | 2 +- > 7 files changed, 57 insertions(+), 22 deletions(-) >
Peter Maydell <peter.maydell@linaro.org> writes: > This pullreq contains fixes for the remaining "not fixed yet" issues > in the 6.0 Planning page: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > None of these are 100% rc4-worthy on their own, but taken all together > I think they justify rolling another release candidate. If you are rolling it would be nice to include: checkpatch: Fix use of uninitialized value Message-Id: <161786467973.295167.5612704777283969903.stgit@bahia.lan> just to avoid the messy warning in the CI checkpatch check. > > thanks > -- PMM > > The following changes since commit 8fe9f1f891eff4e37f82622b7480ee748bf4af74: > > Update version for v6.0.0-rc3 release (2021-04-14 22:06:18 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210417 > > for you to fetch changes up to 277aed998ac2cd3649bf0e13b22f47769519eb61: > > accel/tcg: avoid re-translating one-shot instructions (2021-04-17 18:51:14 +0100) > > ---------------------------------------------------------------- > Fixes for rc4: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > ---------------------------------------------------------------- > Alex Bennée (2): > target/arm: drop CF_LAST_IO/dc->condjump check > accel/tcg: avoid re-translating one-shot instructions > > Paolo Bonzini (2): > osdep: include glib-compat.h before other QEMU headers > osdep: protect qemu/osdep.h with extern "C" > > Peter Maydell (3): > include/qemu/osdep.h: Move system includes to top > hw/arm/armsse: Give SSE-300 its own Property array > hw/arm/armsse: Make SSE-300 use Cortex-M55 > > include/qemu/compiler.h | 6 ++++++ > include/qemu/osdep.h | 38 +++++++++++++++++++++++++++++--------- > accel/tcg/translate-all.c | 2 +- > hw/arm/armsse.c | 24 +++++++++++++++++++----- > target/arm/translate.c | 5 ----- > disas/arm-a64.cc | 2 +- > disas/nanomips.cpp | 2 +- > 7 files changed, 57 insertions(+), 22 deletions(-)
On Sun, 18 Apr 2021 at 17:31, Alex Bennée <alex.bennee@linaro.org> wrote: > > > Peter Maydell <peter.maydell@linaro.org> writes: > > > This pullreq contains fixes for the remaining "not fixed yet" issues > > in the 6.0 Planning page: > > * Fix compile failures of C++ files with new glib headers > > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > > > None of these are 100% rc4-worthy on their own, but taken all together > > I think they justify rolling another release candidate. > > If you are rolling it would be nice to include: > > checkpatch: Fix use of uninitialized value > Message-Id: <161786467973.295167.5612704777283969903.stgit@bahia.lan> > > just to avoid the messy warning in the CI checkpatch check. I always ignore the CI checkpatch check in the github UI anyway :-) -- PMM
On 4/18/21 7:17 AM, Philippe Mathieu-Daudé wrote: > On 4/17/21 9:41 PM, Peter Maydell wrote: >> This pullreq contains fixes for the remaining "not fixed yet" issues >> in the 6.0 Planning page: >> * Fix compile failures of C++ files with new glib headers >> * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU >> * accel/tcg: Fix assertion failure executing from non-RAM with -icount >> >> None of these are 100% rc4-worthy on their own, but taken all together >> I think they justify rolling another release candidate. > > I wonder about this one for https://bugs.launchpad.net/qemu/+bug/1914236 > "mptsas: remove unused MPTSASState.pending (CVE-2021-3392)" > https://www.mail-archive.com/qemu-devel@nongnu.org/msg799236.html > which is a respin of > https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg02660.html > with Paolo's comment addressed. Actualized version: https://www.mail-archive.com/qemu-devel@nongnu.org/msg799620.html This is not a new regression (present since QEMU v2.6.0) but is a CVE...
On 17/04/2021 21.41, Peter Maydell wrote: > This pullreq contains fixes for the remaining "not fixed yet" issues > in the 6.0 Planning page: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > None of these are 100% rc4-worthy on their own, but taken all together > I think they justify rolling another release candidate. FWIW, I'm in favour of adding them, to make sure that QEMU v6.0 also compiles fine on future distros with the new glib headers - this will make debugging easier in the future (e.g. when bisecting or when asking people whether they can check whether a bug already occurred with v6.0 already etc.). Just my 0.02 € of course. Thomas
On Sat, 17 Apr 2021 at 20:42, Peter Maydell <peter.maydell@linaro.org> wrote: > > This pullreq contains fixes for the remaining "not fixed yet" issues > in the 6.0 Planning page: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > > None of these are 100% rc4-worthy on their own, but taken all together > I think they justify rolling another release candidate. > > thanks > -- PMM > > The following changes since commit 8fe9f1f891eff4e37f82622b7480ee748bf4af74: > > Update version for v6.0.0-rc3 release (2021-04-14 22:06:18 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210417 > > for you to fetch changes up to 277aed998ac2cd3649bf0e13b22f47769519eb61: > > accel/tcg: avoid re-translating one-shot instructions (2021-04-17 18:51:14 +0100) > > ---------------------------------------------------------------- > Fixes for rc4: > * Fix compile failures of C++ files with new glib headers > * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU > * accel/tcg: Fix assertion failure executing from non-RAM with -icount > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
This pullreq contains fixes for the remaining "not fixed yet" issues in the 6.0 Planning page: * Fix compile failures of C++ files with new glib headers * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU * accel/tcg: Fix assertion failure executing from non-RAM with -icount None of these are 100% rc4-worthy on their own, but taken all together I think they justify rolling another release candidate. thanks -- PMM The following changes since commit 8fe9f1f891eff4e37f82622b7480ee748bf4af74: Update version for v6.0.0-rc3 release (2021-04-14 22:06:18 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210417 for you to fetch changes up to 277aed998ac2cd3649bf0e13b22f47769519eb61: accel/tcg: avoid re-translating one-shot instructions (2021-04-17 18:51:14 +0100) ---------------------------------------------------------------- Fixes for rc4: * Fix compile failures of C++ files with new glib headers * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU * accel/tcg: Fix assertion failure executing from non-RAM with -icount ---------------------------------------------------------------- Alex Bennée (2): target/arm: drop CF_LAST_IO/dc->condjump check accel/tcg: avoid re-translating one-shot instructions Paolo Bonzini (2): osdep: include glib-compat.h before other QEMU headers osdep: protect qemu/osdep.h with extern "C" Peter Maydell (3): include/qemu/osdep.h: Move system includes to top hw/arm/armsse: Give SSE-300 its own Property array hw/arm/armsse: Make SSE-300 use Cortex-M55 include/qemu/compiler.h | 6 ++++++ include/qemu/osdep.h | 38 +++++++++++++++++++++++++++++--------- accel/tcg/translate-all.c | 2 +- hw/arm/armsse.c | 24 +++++++++++++++++++----- target/arm/translate.c | 5 ----- disas/arm-a64.cc | 2 +- disas/nanomips.cpp | 2 +- 7 files changed, 57 insertions(+), 22 deletions(-)