| Message ID | 20210419060302.14075-1-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: fix vrgather macro index variable type bug | expand |
On 4/18/21 11:03 PM, frank.chang@sifive.com wrote: > From: Frank Chang<frank.chang@sifive.com> > > ETYPE may be type of uint64_t, thus index variable has to be declared as > type of uint64_t, too. Otherwise the value read from vs1 register may be > truncated to type of uint32_t. > > Signed-off-by: Frank Chang<frank.chang@sifive.com> > --- > target/riscv/vector_helper.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d281..4a70776af32 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4796,7 +4796,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t index, i; \ + uint64_t index; \ + uint32_t i; \ \ for (i = 0; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ @@ -4826,7 +4827,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t index = s1, i; \ + uint64_t index = s1; \ + uint32_t i; \ \ for (i = 0; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \