From patchwork Wed Apr 21 04:13:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12215393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BE13C433ED for ; Wed, 21 Apr 2021 04:21:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C72D36140F for ; Wed, 21 Apr 2021 04:21:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C72D36140F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:33522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZ4MM-0007gw-Ub for qemu-devel@archiver.kernel.org; Wed, 21 Apr 2021 00:21:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ4GJ-0007Iy-VZ for qemu-devel@nongnu.org; Wed, 21 Apr 2021 00:14:52 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:39505) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lZ4GF-0003G4-3p for qemu-devel@nongnu.org; Wed, 21 Apr 2021 00:14:51 -0400 Received: by mail-pf1-x42c.google.com with SMTP id c17so27463559pfn.6 for ; Tue, 20 Apr 2021 21:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IgWG1CVoGMCwqvSbgoGbxN9GVciY2DI1Ia/PXIbPLZ4=; b=NbJoVTdQF5tUNllxFP60HkDSCFaU98CoC7XRHYQgN6IJ+eY+nVzRIsQT5TXPAhMaw+ R6xIq0yQMvbgKNl+IrHDf+MxxcQokcMsaL85SvrZ29u2AgRpypwjy13kUaIICjofbvbY hMXZ9x0ix+ngxb73Ily4QVgm2uc6Dx//Ol0hjqYcoWv1vaaK/zZXn7VMxfl31zm/l/WY jDEFfNRdgAcLMYc1KpSoMrZpB6JHy+tuwq7MLlKMToK79SnYlOm0by2yFTsULK3ffynW f68+wSRaZzsmt5dl8FbLxm+MxfD7Qhajq9ldKtVG7GEfgAwDYlUIzC2zfyq3wF/ROgYS Wkrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IgWG1CVoGMCwqvSbgoGbxN9GVciY2DI1Ia/PXIbPLZ4=; b=SrbeJd8Bug+KBue6hZBnju3z9nW1qzPGg+qRRN6VQISg3HW0xBkNULxD6nIfakLTm3 z22D8AigH+vNhKh8gyA15YzePyGB2p2N4MPKSW5L4wurZTbR2XzKFF86eZrExmGNr3D9 85VBlZRWNgKxmSOwkgfJLPM5Zsi49Jv/jKmSjn+O7iS55/4PDB44kx7a28MiG3pqxWuV ct8XG351fGnf2RRLn0E5CF+ZDSuE+YoP2+6n2LMeV+FXiZHJdoNI5dy19bYN3t06CZdh I8WFjYpiwxfVWecT3Bv+GwSAmjAmY/0oO53p0ySC9OlVFDvQDBlW0Ct1YMRIxiusjMFl 81/A== X-Gm-Message-State: AOAM532iErjQPD4dYn1bPiOO7WkxxWJArJ/62fIhkh5BDnvZVNz/aAii bzqg9Rqd3ygt8EaZmTjwf811l9yG+vWyE9u8 X-Google-Smtp-Source: ABdhPJxmH+ptGIKC2s9TjsBkSXIUWpi094d35ZPQRIq+zyDmsnmltvp3QfG4j1kXXqmYlQBOtSDcoA== X-Received: by 2002:a63:5301:: with SMTP id h1mr19679446pgb.109.1618978485546; Tue, 20 Apr 2021 21:14:45 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id jx20sm551465pjb.41.2021.04.20.21.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Apr 2021 21:14:45 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 12/17] target/riscv: rvb: generalized reverse Date: Wed, 21 Apr 2021 12:13:54 +0800 Message-Id: <20210421041400.22243-13-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210421041400.22243-1-frank.chang@sifive.com> References: <20210421041400.22243-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c | 71 +++++++++++++++++++++++++ target/riscv/helper.h | 7 +++ target/riscv/insn32-64.decode | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvb.c.inc | 29 ++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 28 ++++++++++ 7 files changed, 140 insertions(+) create mode 100644 target/riscv/bitmanip_helper.c diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c new file mode 100644 index 00000000000..1d3235bc0d6 --- /dev/null +++ b/target/riscv/bitmanip_helper.c @@ -0,0 +1,71 @@ +/* + * RISC-V Bitmanip Extension Helpers for QEMU. + * + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg.h" + +static const uint64_t adjacent_masks[] = { + dup_const(MO_8, 0x55), + dup_const(MO_8, 0x33), + dup_const(MO_8, 0x0f), + dup_const(MO_16, 0xff), + dup_const(MO_32, 0xffff), +#ifdef TARGET_RISCV64 + UINT32_MAX +#endif +}; + +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift) +{ + return ((x & mask) << shift) | ((x & ~mask) >> shift); +} + +static target_ulong do_grev(target_ulong rs1, + target_ulong rs2, + int bits) +{ + target_ulong x = rs1; + int i, shift; + + for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) { + if (rs2 & shift) { + x = do_swap(x, adjacent_masks[i], shift); + } + } + + return x; +} + +target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2) +{ + return do_grev(rs1, rs2, TARGET_LONG_BITS); +} + +/* RV64-only instruction */ +#ifdef TARGET_RISCV64 + +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2) +{ + return do_grev(rs1, rs2, 32); +} + +#endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e3f3f41e891..db8b770f1aa 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -58,6 +58,13 @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) +/* Bitmanip */ +DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) + +#if defined(TARGET_RISCV64) +DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif + /* Special functions */ DEF_HELPER_3(csrrw, tl, env, tl, tl) DEF_HELPER_4(csrrs, tl, env, tl, tl, tl) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 8f9ba21b352..38ceadd4553 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -102,6 +102,7 @@ slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r +grevw 0110100 .......... 101 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -109,3 +110,4 @@ binviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 +greviw 0110100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6d1b604c800..fa4bba4f0ee 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -619,6 +619,7 @@ slo 0010000 .......... 001 ..... 0110011 @r sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r +grev 0110100 .......... 101 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -627,3 +628,4 @@ bexti 01001. ........... 101 ..... 0010011 @sh sloi 00100. ........... 001 ..... 0010011 @sh sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh +grevi 01101. ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 8a46fde4767..286643cd183 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -197,6 +197,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, tcg_gen_rotl_tl); } +static bool trans_grev(DisasContext *ctx, arg_grev *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_helper_grev); +} + +static bool trans_grevi(DisasContext *ctx, arg_grevi *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + return gen_grevi(ctx, a); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -314,4 +331,16 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) return gen_shiftw(ctx, a, gen_rolw); } +static bool trans_grevw(DisasContext *ctx, arg_grevw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_grevw); +} + +static bool trans_greviw(DisasContext *ctx, arg_greviw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_grevw); +} + #endif diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 88ab8506821..f7f921ab491 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -21,6 +21,7 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'bitmanip_helper.c', 'translate.c', )) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5f62fbb6964..e47bae3ab2b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -615,6 +615,28 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_not_tl(ret, ret); } +static bool gen_grevi(DisasContext *ctx, arg_grevi *a) +{ + TCGv source1 = tcg_temp_new(); + TCGv source2; + + gen_get_gpr(source1, a->rs1); + + if (a->shamt == (TARGET_LONG_BITS - 8)) { + /* rev8, byte swaps */ + tcg_gen_bswap_tl(source1, source1); + } else { + source2 = tcg_temp_new(); + tcg_gen_movi_tl(source2, a->shamt); + gen_helper_grev(source1, source1, source2); + tcg_temp_free(source2); + } + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + return true; +} + #ifdef TARGET_RISCV64 static void gen_ctzw(TCGv ret, TCGv arg1) @@ -689,6 +711,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free_i32(t2); } +static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + gen_helper_grev(ret, arg1, arg2); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a,