| Message ID | 20210421133236.11323-1-emmanuel.blot@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: fix a typo with interrupt names | expand |
On Wed, Apr 21, 2021 at 11:33 PM Emmanuel Blot <emmanuel.blot@sifive.com> wrote: > > Interrupt names have been swapped in 205377f8 and do not follow > IRQ_*_EXT definition order. > > Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7d6ed80f6b6..c79503ce967 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = { > "vs_timer", > "m_timer", > "u_external", > + "s_external", > "vs_external", > - "h_external", > "m_external", > "reserved", > "reserved", > -- > 2.31.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b6..c79503ce967 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = { "vs_timer", "m_timer", "u_external", + "s_external", "vs_external", - "h_external", "m_external", "reserved", "reserved",
Interrupt names have been swapped in 205377f8 and do not follow IRQ_*_EXT definition order. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)