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Tue, 27 Apr 2021 15:06:27 -0700 (PDT) Received: from neptune.lab ([46.39.228.82]) by smtp.googlemail.com with ESMTPSA id r10sm640049ejd.112.2021.04.27.15.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Apr 2021 15:06:27 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Date: Wed, 28 Apr 2021 01:06:15 +0300 Message-Id: <20210427220615.12763-7-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210427220615.12763-1-space.monkey.delivers@gmail.com> References: <20210427220615.12763-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0682410f5d..fecc64d7ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY env->mmte |= PM_EXT_INITIAL; #endif + target_misa |= RVJ; } if (cpu->cfg.ext_v) { target_misa |= RVV; @@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),