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03 May 2021 14:55:15 -0700 IronPort-SDR: 5usfdQ4BQo0E4fGX+1QuQ2z3/4Ly4CGsQ7YkI3Em9/0qe9fiZci2YxNvZPcxVPQH+UE3dn/ihN fV9ozQvLS/gh4DvLrE0z0/Bz0fjh/cQrEObtwvoTplUjPEUc/IDRaRBzrUtqEFEZZpsPWBDX8u g26d/F+263DZUJGQXPadtiK1yC8M33cwBwDCYc9swUVKXTE7kd+AxCs5rhb1FPUwQHscuM9zom Og6x560Xq6z0vtLEswso1PjWSZd+48dCRviipPPmg4S481q7HruJN0c9Gjak0KYCz3Lbwbvwjj tko= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.45]) by uls-op-cesaip01.wdc.com with ESMTP; 03 May 2021 15:15:01 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 25/42] target/riscv: Add a config option for ePMP Date: Tue, 4 May 2021 08:13:10 +1000 Message-Id: <20210503221327.3068768-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210503221327.3068768-1-alistair.francis@wdc.com> References: <20210503221327.3068768-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=750139ea6=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , qemu-devel@nongnu.org, Hongzheng-Li , Alistair Francis , alistair23@gmail.com, Bin Meng , Myriad-Dreamin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Hou Weiying Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 83b315e0b2..add734bbbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,7 @@ struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + bool epmp; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e530df9385..66787d019c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -412,6 +412,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.pmp) { set_feature(env, RISCV_FEATURE_PMP); + + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + if (cpu->cfg.epmp) { + set_feature(env, RISCV_FEATURE_EPMP); + } } set_resetvec(env, cpu->cfg.resetvec); @@ -554,6 +562,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), };