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03 May 2021 14:55:27 -0700 IronPort-SDR: IQCzi7MJ3s6kq/BpPdfZEJeT6ne0gJ2NZIosFiraCRSfizHhnXNueB1D8CV+wIsR3szXrKTfvb 1BNuSBw8FayCNyblf/cTtvMWXTyxTzCPiOWRKDaQiofVk4dHP2bs7LpuiDnue38NhlMfmqBJqu Gnee/ZN+RLCI3lml/KlqVz75saT4aDUNAukdGxAu6b9rNqFhHP6L5cqU3ovtiXZ634nm0uBwpp atGVKjd/gRUaxAsJ5BBO05d6UQHl/01qGv7i0Bro0JG+7aErVerDGvyZJ+1Qlh58J/u1z2lE8a Uw8= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.45]) by uls-op-cesaip01.wdc.com with ESMTP; 03 May 2021 15:15:14 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 29/42] target/riscv: fix exception index on instruction access fault Date: Tue, 4 May 2021 08:13:14 +1000 Message-Id: <20210503221327.3068768-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210503221327.3068768-1-alistair.francis@wdc.com> References: <20210503221327.3068768-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=750139ea6=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Emmanuel Blot Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Emmanuel Blot When no MMU is used and the guest code attempts to fetch an instruction from an invalid memory location, the exception index defaults to a data load access fault, rather an instruction access fault. Signed-off-by: Emmanuel Blot Reviewed-by: Alistair Francis Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 659ca8a173..1018c0036d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type == MMU_DATA_LOAD) { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; } env->badaddr = addr;