| Message ID | 20210505160620.15723-11-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of bitmanip extension | expand |
On Thu, May 6, 2021 at 2:08 AM <frank.chang@sifive.com> wrote: > > From: Kito Cheng <kito.cheng@sifive.com> > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn32.decode | 8 ++++ > target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++ > target/riscv/translate.c | 14 +++++++ > 3 files changed, 74 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 433b601b934..6bc9bbae9e0 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r > bclr 0100100 .......... 001 ..... 0110011 @r > binv 0110100 .......... 001 ..... 0110011 @r > bext 0100100 .......... 101 ..... 0110011 @r > +slo 0010000 .......... 001 ..... 0110011 @r > +sro 0010000 .......... 101 ..... 0110011 @r > > bseti 00101. ........... 001 ..... 0010011 @sh > bclri 01001. ........... 001 ..... 0010011 @sh > binvi 01101. ........... 001 ..... 0010011 @sh > bexti 01001. ........... 101 ..... 0010011 @sh > +sloi 00100. ........... 001 ..... 0010011 @sh > +sroi 00100. ........... 101 ..... 0010011 @sh > > # *** RV64B Standard Extension (in addition to RV32B) *** > clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > @@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r > bclrw 0100100 .......... 001 ..... 0111011 @r > binvw 0110100 .......... 001 ..... 0111011 @r > bextw 0100100 .......... 101 ..... 0111011 @r > +slow 0010000 .......... 001 ..... 0111011 @r > +srow 0010000 .......... 101 ..... 0111011 @r > > bsetiw 0010100 .......... 001 ..... 0011011 @sh5 > bclriw 0100100 .......... 001 ..... 0011011 @sh5 > binviw 0110100 .......... 001 ..... 0011011 @sh5 > +sloiw 0010000 .......... 001 ..... 0011011 @sh5 > +sroiw 0010000 .......... 101 ..... 0011011 @sh5 > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index 69e5af44a18..28640322c43 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) > return gen_shifti(ctx, a, gen_bext); > } > > +static bool trans_slo(DisasContext *ctx, arg_slo *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, gen_slo); > +} > + > +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shifti(ctx, a, gen_slo); > +} > + > +static bool trans_sro(DisasContext *ctx, arg_sro *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, gen_sro); > +} > + > +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shifti(ctx, a, gen_sro); > +} > + > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > @@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a) > REQUIRE_EXT(ctx, RVB); > return gen_shiftw(ctx, a, gen_bext); > } > + > +static bool trans_slow(DisasContext *ctx, arg_slow *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_slo); > +} > + > +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftiw(ctx, a, gen_slo); > +} > + > +static bool trans_srow(DisasContext *ctx, arg_srow *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_sro); > +} > + > +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftiw(ctx, a, gen_sro); > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index e12240d1255..088cf9f7678 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) > tcg_gen_andi_tl(ret, ret, 1); > } > > +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + tcg_gen_not_tl(ret, arg1); > + tcg_gen_shl_tl(ret, ret, arg2); > + tcg_gen_not_tl(ret, ret); > +} > + > +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + tcg_gen_not_tl(ret, arg1); > + tcg_gen_shr_tl(ret, ret, arg2); > + tcg_gen_not_tl(ret, ret); > +} > + > static void gen_ctzw(TCGv ret, TCGv arg1) > { > tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); > -- > 2.17.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 433b601b934..6bc9bbae9e0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r +slo 0010000 .......... 001 ..... 0110011 @r +sro 0010000 .......... 101 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh +sloi 00100. ........... 001 ..... 0010011 @sh +sroi 00100. ........... 101 ..... 0010011 @sh # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r bclrw 0100100 .......... 001 ..... 0111011 @r binvw 0110100 .......... 001 ..... 0111011 @r bextw 0100100 .......... 101 ..... 0111011 @r +slow 0010000 .......... 001 ..... 0111011 @r +srow 0010000 .......... 101 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 binviw 0110100 .......... 001 ..... 0011011 @sh5 +sloiw 0010000 .......... 001 ..... 0011011 @sh5 +sroiw 0010000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 69e5af44a18..28640322c43 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_sro); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a) REQUIRE_EXT(ctx, RVB); return gen_shiftw(ctx, a, gen_bext); } + +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_slo); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_slo); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_sro); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_sro); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e12240d1255..088cf9f7678 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shl_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shr_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + static void gen_ctzw(TCGv ret, TCGv arg1) { tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));