| Message ID | 20210505160620.15723-12-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of bitmanip extension | expand |
On Thu, May 6, 2021 at 2:17 AM <frank.chang@sifive.com> wrote: > > From: Kito Cheng <kito.cheng@sifive.com> > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn32.decode | 6 ++++ > target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++ > target/riscv/translate.c | 36 +++++++++++++++++++++++ > 3 files changed, 81 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 6bc9bbae9e0..71a9a182c01 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r > bext 0100100 .......... 101 ..... 0110011 @r > slo 0010000 .......... 001 ..... 0110011 @r > sro 0010000 .......... 101 ..... 0110011 @r > +ror 0110000 .......... 101 ..... 0110011 @r > +rol 0110000 .......... 001 ..... 0110011 @r > > bseti 00101. ........... 001 ..... 0010011 @sh > bclri 01001. ........... 001 ..... 0010011 @sh > @@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh > bexti 01001. ........... 101 ..... 0010011 @sh > sloi 00100. ........... 001 ..... 0010011 @sh > sroi 00100. ........... 101 ..... 0010011 @sh > +rori 01100. ........... 101 ..... 0010011 @sh > > # *** RV64B Standard Extension (in addition to RV32B) *** > clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > @@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r > bextw 0100100 .......... 101 ..... 0111011 @r > slow 0010000 .......... 001 ..... 0111011 @r > srow 0010000 .......... 101 ..... 0111011 @r > +rorw 0110000 .......... 101 ..... 0111011 @r > +rolw 0110000 .......... 001 ..... 0111011 @r > > bsetiw 0010100 .......... 001 ..... 0011011 @sh5 > bclriw 0100100 .......... 001 ..... 0011011 @sh5 > binviw 0110100 .......... 001 ..... 0011011 @sh5 > sloiw 0010000 .......... 001 ..... 0011011 @sh5 > sroiw 0010000 .......... 101 ..... 0011011 @sh5 > +roriw 0110000 .......... 101 ..... 0011011 @sh5 > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index 28640322c43..429738db155 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a) > return gen_shifti(ctx, a, gen_sro); > } > > +static bool trans_ror(DisasContext *ctx, arg_ror *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, tcg_gen_rotr_tl); > +} > + > +static bool trans_rori(DisasContext *ctx, arg_rori *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shifti(ctx, a, tcg_gen_rotr_tl); > +} > + > +static bool trans_rol(DisasContext *ctx, arg_rol *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_shift(ctx, a, tcg_gen_rotl_tl); > +} > + > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) > REQUIRE_EXT(ctx, RVB); > return gen_shiftiw(ctx, a, gen_sro); > } > + > +static bool trans_rorw(DisasContext *ctx, arg_rorw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_rorw); > +} > + > +static bool trans_roriw(DisasContext *ctx, arg_roriw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftiw(ctx, a, gen_rorw); > +} > + > +static bool trans_rolw(DisasContext *ctx, arg_rolw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_shiftw(ctx, a, gen_rolw); > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 088cf9f7678..c09b93f1b8a 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) > tcg_temp_free(t); > } > > +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + TCGv_i32 t1 = tcg_temp_new_i32(); > + TCGv_i32 t2 = tcg_temp_new_i32(); > + > + /* truncate to 32-bits */ > + tcg_gen_trunc_tl_i32(t1, arg1); > + tcg_gen_trunc_tl_i32(t2, arg2); > + > + tcg_gen_rotr_i32(t1, t1, t2); > + > + /* sign-extend 64-bits */ > + tcg_gen_ext_i32_tl(ret, t1); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(t2); > +} > + > +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) > +{ > + TCGv_i32 t1 = tcg_temp_new_i32(); > + TCGv_i32 t2 = tcg_temp_new_i32(); > + > + /* truncate to 32-bits */ > + tcg_gen_trunc_tl_i32(t1, arg1); > + tcg_gen_trunc_tl_i32(t2, arg2); > + > + tcg_gen_rotl_i32(t1, t1, t2); > + > + /* sign-extend 64-bits */ > + tcg_gen_ext_i32_tl(ret, t1); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(t2); > +} > + > static bool gen_arith(DisasContext *ctx, arg_r *a, > void(*func)(TCGv, TCGv, TCGv)) > { > -- > 2.17.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6bc9bbae9e0..71a9a182c01 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r slo 0010000 .......... 001 ..... 0110011 @r sro 0010000 .......... 101 ..... 0110011 @r +ror 0110000 .......... 101 ..... 0110011 @r +rol 0110000 .......... 001 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh sloi 00100. ........... 001 ..... 0010011 @sh sroi 00100. ........... 101 ..... 0010011 @sh +rori 01100. ........... 101 ..... 0010011 @sh # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r bextw 0100100 .......... 101 ..... 0111011 @r slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r +rorw 0110000 .......... 101 ..... 0111011 @r +rolw 0110000 .......... 001 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 binviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 +roriw 0110000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 28640322c43..429738db155 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a) return gen_shifti(ctx, a, gen_sro); } +static bool trans_ror(DisasContext *ctx, arg_ror *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, tcg_gen_rotr_tl); +} + +static bool trans_rori(DisasContext *ctx, arg_rori *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, tcg_gen_rotr_tl); +} + +static bool trans_rol(DisasContext *ctx, arg_rol *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, tcg_gen_rotl_tl); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) REQUIRE_EXT(ctx, RVB); return gen_shiftiw(ctx, a, gen_sro); } + +static bool trans_rorw(DisasContext *ctx, arg_rorw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_rorw); +} + +static bool trans_roriw(DisasContext *ctx, arg_roriw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_rorw); +} + +static bool trans_rolw(DisasContext *ctx, arg_rolw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_rolw); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 088cf9f7678..c09b93f1b8a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) {