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[122.116.72.36]) by smtp.gmail.com with ESMTPSA id js6sm35877977pjb.0.2021.05.05.09.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 09:07:26 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line Date: Thu, 6 May 2021 00:06:17 +0800 Message-Id: <20210505160620.15723-17-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> References: <20210505160620.15723-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Kito Cheng , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Kito Cheng B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3191fd00822..1b3c5ba1480 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -486,6 +486,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -556,6 +559,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f95bcbd8e10..3cea62cd4c4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -284,6 +284,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h;