| Message ID | 20210505160620.15723-3-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of bitmanip extension | expand |
On Thu, May 6, 2021 at 2:24 AM <frank.chang@sifive.com> wrote: > > From: Kito Cheng <kito.cheng@sifive.com> > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 11 ++++++- > target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++ > target/riscv/translate.c | 38 +++++++++++++++++++++ > 4 files changed, 93 insertions(+), 1 deletion(-) > create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7e879fb9ca5..f95bcbd8e10 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -67,6 +67,7 @@ > #define RVS RV('S') > #define RVU RV('U') > #define RVH RV('H') > +#define RVB RV('B') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index f75642bb0d2..9a2ffab1504 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -41,6 +41,7 @@ > &i imm rs1 rd > &j imm rd > &r rd rs1 rs2 > +&r2 rd rs1 > &s imm rs1 rs2 > &u imm rd > &shift shamt rs1 rd > @@ -68,7 +69,7 @@ > @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd > @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd > @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd > -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd > +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd > @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd > @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd > @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd > @@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm > vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm > vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm > vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm > + > +# *** RV32B Standard Extension *** > +clz 011000 000000 ..... 001 ..... 0010011 @r2 > +ctz 011000 000001 ..... 001 ..... 0010011 @r2 > + > +# *** RV64B Standard Extension (in addition to RV32B) *** > +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > new file mode 100644 > index 00000000000..157b4e3c41d > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -0,0 +1,44 @@ > +/* > + * RISC-V translation routines for the RVB Standard Extension. > + * > + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com > + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +static bool trans_clz(DisasContext *ctx, arg_clz *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, gen_clz); > +} > + > +static bool trans_ctz(DisasContext *ctx, arg_ctz *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, gen_ctz); > +} > + > +static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, gen_clzw); > +} > + > +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, gen_ctzw); > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index e945352bca3..60fac0fe27e 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, > return true; > } > > +static void gen_ctzw(TCGv ret, TCGv arg1) > +{ > + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); > + tcg_gen_ctzi_tl(ret, ret, 64); > +} > + > +static void gen_clzw(TCGv ret, TCGv arg1) > +{ > + tcg_gen_ext32u_tl(ret, arg1); > + tcg_gen_clzi_tl(ret, ret, 64); > + tcg_gen_subi_tl(ret, ret, 32); > +} > + > static bool gen_arith(DisasContext *ctx, arg_r *a, > void(*func)(TCGv, TCGv, TCGv)) > { > @@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > return cpu_ldl_code(env, pc); > } > > +static void gen_ctz(TCGv ret, TCGv arg1) > +{ > + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); > +} > + > +static void gen_clz(TCGv ret, TCGv arg1) > +{ > + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); > +} > + > +static bool gen_unary(DisasContext *ctx, arg_r2 *a, > + void(*func)(TCGv, TCGv)) > +{ > + TCGv source = tcg_temp_new(); > + > + gen_get_gpr(source, a->rs1); > + > + (*func)(source, source); > + > + gen_set_gpr(a->rd, source); > + tcg_temp_free(source); > + return true; > +} > + > /* Include insn module translation function */ > #include "insn_trans/trans_rvi.c.inc" > #include "insn_trans/trans_rvm.c.inc" > @@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvd.c.inc" > #include "insn_trans/trans_rvh.c.inc" > #include "insn_trans/trans_rvv.c.inc" > +#include "insn_trans/trans_rvb.c.inc" > #include "insn_trans/trans_privileged.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > -- > 2.17.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7e879fb9ca5..f95bcbd8e10 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVB RV('B') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f75642bb0d2..9a2ffab1504 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -41,6 +41,7 @@ &i imm rs1 rd &j imm rd &r rd rs1 rs2 +&r2 rd rs1 &s imm rs1 rs2 &u imm rd &shift shamt rs1 rd @@ -68,7 +69,7 @@ @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm + +# *** RV32B Standard Extension *** +clz 011000 000000 ..... 001 ..... 0010011 @r2 +ctz 011000 000001 ..... 001 ..... 0010011 @r2 + +# *** RV64B Standard Extension (in addition to RV32B) *** +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc new file mode 100644 index 00000000000..157b4e3c41d --- /dev/null +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -0,0 +1,44 @@ +/* + * RISC-V translation routines for the RVB Standard Extension. + * + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_clz(DisasContext *ctx, arg_clz *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_clz); +} + +static bool trans_ctz(DisasContext *ctx, arg_ctz *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_ctz); +} + +static bool trans_clzw(DisasContext *ctx, arg_clzw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_clzw); +} + +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_ctzw); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e945352bca3..60fac0fe27e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, return true; } +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); + tcg_gen_ctzi_tl(ret, ret, 64); +} + +static void gen_clzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(ret, arg1); + tcg_gen_clzi_tl(ret, ret, 64); + tcg_gen_subi_tl(ret, ret, 32); +} + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { @@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) return cpu_ldl_code(env, pc); } +static void gen_ctz(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); +} + +static void gen_clz(TCGv ret, TCGv arg1) +{ + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); +} + +static bool gen_unary(DisasContext *ctx, arg_r2 *a, + void(*func)(TCGv, TCGv)) +{ + TCGv source = tcg_temp_new(); + + gen_get_gpr(source, a->rs1); + + (*func)(source, source); + + gen_set_gpr(a->rd, source); + tcg_temp_free(source); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" @@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvd.c.inc" #include "insn_trans/trans_rvh.c.inc" #include "insn_trans/trans_rvv.c.inc" +#include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */