diff mbox series

[PULL,v2,39/42] target/riscv: Remove an unused CASE_OP_32_64 macro

Message ID 20210505232312.4175486-40-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code | expand

Commit Message

Alistair Francis May 5, 2021, 11:23 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/translate.c | 6 ------
 1 file changed, 6 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a596f80f20..a1f794ffda 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,12 +67,6 @@  typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-#define CASE_OP_32_64(X) case X: case glue(X, W)
-#else
-#define CASE_OP_32_64(X) case X
-#endif
-
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 {
     return ctx->misa & ext;