| Message ID | 20210517205025.3777947-12-matheus.ferst@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Base for adding PowerPC 64-bit instructions | expand |
On Mon, May 17, 2021 at 05:50:13PM -0300, matheus.ferst@eldorado.org.br wrote: > From: Richard Henderson <richard.henderson@linaro.org> > > Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Applied to ppc-for-6.1, thanks. > --- > target/ppc/cpu.h | 1 + > target/ppc/insn32.decode | 18 ++++++++++++ > target/ppc/insn64.decode | 18 ++++++++++++ > target/ppc/meson.build | 9 ++++++ > target/ppc/translate.c | 34 +++++++++++++++++++--- > target/ppc/translate/fixedpoint-impl.c.inc | 18 ++++++++++++ > 6 files changed, 94 insertions(+), 4 deletions(-) > create mode 100644 target/ppc/insn32.decode > create mode 100644 target/ppc/insn64.decode > create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index cab33a3680..351fcdf5f8 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -144,6 +144,7 @@ enum { > POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ > POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ > POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ > + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ > /* Exception subtypes for POWERPC_EXCP_PROGRAM */ > /* FP exceptions */ > POWERPC_EXCP_FP = 0x10, > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > new file mode 100644 > index 0000000000..a3a8ae06bf > --- /dev/null > +++ b/target/ppc/insn32.decode > @@ -0,0 +1,18 @@ > +# > +# Power ISA decode for 32-bit insns (opcode space 0) > +# > +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) > +# > +# This library is free software; you can redistribute it and/or > +# modify it under the terms of the GNU Lesser General Public > +# License as published by the Free Software Foundation; either > +# version 2.1 of the License, or (at your option) any later version. > +# > +# This library is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > +# Lesser General Public License for more details. > +# > +# You should have received a copy of the GNU Lesser General Public > +# License along with this library; if not, see <http://www.gnu.org/licenses/>. > +# > diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode > new file mode 100644 > index 0000000000..a38b1f84dc > --- /dev/null > +++ b/target/ppc/insn64.decode > @@ -0,0 +1,18 @@ > +# > +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) > +# > +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) > +# > +# This library is free software; you can redistribute it and/or > +# modify it under the terms of the GNU Lesser General Public > +# License as published by the Free Software Foundation; either > +# version 2.1 of the License, or (at your option) any later version. > +# > +# This library is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > +# Lesser General Public License for more details. > +# > +# You should have received a copy of the GNU Lesser General Public > +# License along with this library; if not, see <http://www.gnu.org/licenses/>. > +# > diff --git a/target/ppc/meson.build b/target/ppc/meson.build > index d1aa7d5d39..512e3a0288 100644 > --- a/target/ppc/meson.build > +++ b/target/ppc/meson.build > @@ -17,6 +17,15 @@ ppc_ss.add(files( > > ppc_ss.add(libdecnumber) > > +gen = [ > + decodetree.process('insn32.decode', > + extra_args: '--static-decode=decode_insn32'), > + decodetree.process('insn64.decode', > + extra_args: ['--static-decode=decode_insn64', > + '--insnwidth=64']), > +] > +ppc_ss.add(gen) > + > ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) > ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index b1873d2dcc..64d6acb078 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) > # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) > #endif > > +#include "decode-insn32.c.inc" > +#include "decode-insn64.c.inc" > +#include "translate/fixedpoint-impl.c.inc" > + > #include "translate/fp-impl.c.inc" > > #include "translate/vmx-impl.c.inc" > @@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, > return true; > } > > +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) > +{ > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > + return opc1(insn) == 1; > +} > + > static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > PowerPCCPU *cpu = POWERPC_CPU(cs); > CPUPPCState *env = cs->env_ptr; > + target_ulong pc; > uint32_t insn; > bool ok; > > @@ -9101,11 +9112,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) > LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", > ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); > > - ctx->cia = ctx->base.pc_next; > - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); > - ctx->base.pc_next += 4; > + ctx->cia = pc = ctx->base.pc_next; > + insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); > + ctx->base.pc_next = pc += 4; > > - ok = decode_legacy(cpu, ctx, insn); > + if (!is_prefix_insn(ctx, insn)) { > + ok = (decode_insn32(ctx, insn) || > + decode_legacy(cpu, ctx, insn)); > + } else if ((pc & 63) == 0) { > + /* > + * Power v3.1, section 1.9 Exceptions: > + * attempt to execute a prefixed instruction that crosses a > + * 64-byte address boundary (system alignment error). > + */ > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); > + ok = true; > + } else { > + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); > + ctx->base.pc_next = pc += 4; > + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); > + } > if (!ok) { > gen_invalid(ctx); > } > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > new file mode 100644 > index 0000000000..be75085cee > --- /dev/null > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -0,0 +1,18 @@ > +/* > + * Power ISA decode for Fixed-Point Facility instructions > + * > + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see <http://www.gnu.org/licenses/>. > + */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cab33a3680..351fcdf5f8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -144,6 +144,7 @@ enum { POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ /* Exception subtypes for POWERPC_EXCP_PROGRAM */ /* FP exceptions */ POWERPC_EXCP_FP = 0x10, diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode new file mode 100644 index 0000000000..a3a8ae06bf --- /dev/null +++ b/target/ppc/insn32.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 32-bit insns (opcode space 0) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see <http://www.gnu.org/licenses/>. +# diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode new file mode 100644 index 0000000000..a38b1f84dc --- /dev/null +++ b/target/ppc/insn64.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see <http://www.gnu.org/licenses/>. +# diff --git a/target/ppc/meson.build b/target/ppc/meson.build index d1aa7d5d39..512e3a0288 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -17,6 +17,15 @@ ppc_ss.add(files( ppc_ss.add(libdecnumber) +gen = [ + decodetree.process('insn32.decode', + extra_args: '--static-decode=decode_insn32'), + decodetree.process('insn64.decode', + extra_args: ['--static-decode=decode_insn64', + '--insnwidth=64']), +] +ppc_ss.add(gen) + ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b1873d2dcc..64d6acb078 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +#include "decode-insn32.c.inc" +#include "decode-insn64.c.inc" +#include "translate/fixedpoint-impl.c.inc" + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" @@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, return true; } +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + return opc1(insn) == 1; +} + static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = cs->env_ptr; + target_ulong pc; uint32_t insn; bool ok; @@ -9101,11 +9112,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); - ctx->cia = ctx->base.pc_next; - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); - ctx->base.pc_next += 4; + ctx->cia = pc = ctx->base.pc_next; + insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; - ok = decode_legacy(cpu, ctx, insn); + if (!is_prefix_insn(ctx, insn)) { + ok = (decode_insn32(ctx, insn) || + decode_legacy(cpu, ctx, insn)); + } else if ((pc & 63) == 0) { + /* + * Power v3.1, section 1.9 Exceptions: + * attempt to execute a prefixed instruction that crosses a + * 64-byte address boundary (system alignment error). + */ + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); + ok = true; + } else { + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); + } if (!ok) { gen_invalid(ctx); } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc new file mode 100644 index 0000000000..be75085cee --- /dev/null +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,18 @@ +/* + * Power ISA decode for Fixed-Point Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */