| Message ID | 20210517205025.3777947-20-matheus.ferst@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Base for adding PowerPC 64-bit instructions | expand |
On Mon, May 17, 2021 at 05:50:21PM -0300, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst <matheus.ferst@eldorado.org.br> > > Implements the following PowerISA v3.1 instructions: > setbc: Set Boolean Condition > setbcr: Set Boolean Condition Reverse > setnbc: Set Negative Boolean Condition > setnbcr: Set Negative Boolean Condition Reverse > > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Applied to ppc-for-6.1, thanks. > --- > v5: > - Style fix; > - Use tcg_gen_setcondi_tl instead of tcg_gen_movcond_tl. > --- > target/ppc/insn32.decode | 10 ++++++++++ > target/ppc/translate/fixedpoint-impl.c.inc | 23 ++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 00ec0f4328..bc69c70493 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -26,6 +26,9 @@ > &X rt ra rb > @X ...... rt:5 ra:5 rb:5 .......... . &X > > +&X_bi rt bi > +@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi > + > ### Fixed-Point Load Instructions > > LBZ 100010 ..... ..... ................ @D > @@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X > > ADDI 001110 ..... ..... ................ @D > ADDIS 001111 ..... ..... ................ @D > + > +### Move To/From System Register Instructions > + > +SETBC 011111 ..... ..... ----- 0110000000 - @X_bi > +SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi > +SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi > +SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index 2d2d874146..204848d017 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) > { > return true; > } > + > +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) > +{ > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > + uint32_t mask = 0x08 >> (a->bi & 0x03); > + TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE; > + TCGv temp = tcg_temp_new(); > + > + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); > + tcg_gen_andi_tl(temp, temp, mask); > + tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0); > + if(neg) { > + tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]); > + } > + tcg_temp_free(temp); > + > + return true; > +} > + > +TRANS(SETBC, do_set_bool_cond, false, false) > +TRANS(SETBCR, do_set_bool_cond, false, true) > +TRANS(SETNBC, do_set_bool_cond, true, false) > +TRANS(SETNBCR, do_set_bool_cond, true, true)
On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> + if(neg) {
Missing space.
r~
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 00ec0f4328..bc69c70493 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -26,6 +26,9 @@ &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X +&X_bi rt bi +@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi + ### Fixed-Point Load Instructions LBZ 100010 ..... ..... ................ @D @@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D + +### Move To/From System Register Instructions + +SETBC 011111 ..... ..... ----- 0110000000 - @X_bi +SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi +SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi +SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 2d2d874146..204848d017 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) { return true; } + +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + uint32_t mask = 0x08 >> (a->bi & 0x03); + TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE; + TCGv temp = tcg_temp_new(); + + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); + tcg_gen_andi_tl(temp, temp, mask); + tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0); + if(neg) { + tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]); + } + tcg_temp_free(temp); + + return true; +} + +TRANS(SETBC, do_set_bool_cond, false, false) +TRANS(SETBCR, do_set_bool_cond, false, true) +TRANS(SETNBC, do_set_bool_cond, true, false) +TRANS(SETNBCR, do_set_bool_cond, true, true)