diff mbox series

target/ppc: Fix load endianness for lxvwsx/lxvdsx

Message ID 20210518092352.43610-1-thatlemon@gmail.com (mailing list archive)
State New, archived
Headers show
Series target/ppc: Fix load endianness for lxvwsx/lxvdsx | expand

Commit Message

Giuseppe Musacchio May 18, 2021, 9:23 a.m. UTC 
TARGET_WORDS_BIGENDIAN may not match the machine endianness if that's a
runtime-configurable parameter.

Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/212

Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
---
 target/ppc/translate/vsx-impl.c.inc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Comments

Greg Kurz May 18, 2021, 10:37 a.m. UTC | #1 
On Tue, 18 May 2021 11:23:52 +0200
Giuseppe Musacchio <thatlemon@gmail.com> wrote:

> TARGET_WORDS_BIGENDIAN may not match the machine endianness if that's a
> runtime-configurable parameter.
> 
> Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c

and

Fixes: afae37d98ae991c0792c867dbd9f32f988044318

for lxvwsx.

Reviewed-by: Greg Kurz <groug@kaod.org>

Cc'ing qemu-stable since this looks like a regression of QEMU 6.0.

> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/212
> 
> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> ---
>  target/ppc/translate/vsx-impl.c.inc | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
> index b817d31260..3e840e756f 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -139,7 +139,11 @@ static void gen_lxvwsx(DisasContext *ctx)
>      gen_addr_reg_index(ctx, EA);
>  
>      data = tcg_temp_new_i32();
> -    tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
> +    if (ctx->le_mode) {
> +        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_LEUL);
> +    } else {
> +        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_BEUL);
> +    }
>      tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
>  
>      tcg_temp_free(EA);
> @@ -162,7 +166,11 @@ static void gen_lxvdsx(DisasContext *ctx)
>      gen_addr_reg_index(ctx, EA);
>  
>      data = tcg_temp_new_i64();
> -    tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
> +    if (ctx->le_mode) {
> +        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_LEQ);
> +    } else {
> +        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_BEQ);
> +    }
>      tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
>  
>      tcg_temp_free(EA);
Richard Henderson May 18, 2021, 10:42 a.m. UTC | #2 
On 5/18/21 4:23 AM, Giuseppe Musacchio wrote:
> TARGET_WORDS_BIGENDIAN may not match the machine endianness if that's a
> runtime-configurable parameter.
> 
> Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/212
> 
> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> ---
>   target/ppc/translate/vsx-impl.c.inc | 12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
> index b817d31260..3e840e756f 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -139,7 +139,11 @@ static void gen_lxvwsx(DisasContext *ctx)
>       gen_addr_reg_index(ctx, EA);
>   
>       data = tcg_temp_new_i32();
> -    tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
> +    if (ctx->le_mode) {
> +        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_LEUL);
> +    } else {
> +        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_BEUL);
> +    }

Reducing this replication is why we have default_tcg_memop_mask.

This should be ctx->default_tcg_memop_mask | MO_UL.

>       tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
>   
>       tcg_temp_free(EA);
> @@ -162,7 +166,11 @@ static void gen_lxvdsx(DisasContext *ctx)
>       gen_addr_reg_index(ctx, EA);
>   
>       data = tcg_temp_new_i64();
> -    tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
> +    if (ctx->le_mode) {
> +        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_LEQ);
> +    } else {
> +        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_BEQ);
> +    }

Similarly ... | MO_Q.


r~
diff mbox series

Patch

diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b817d31260..3e840e756f 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -139,7 +139,11 @@  static void gen_lxvwsx(DisasContext *ctx)
     gen_addr_reg_index(ctx, EA);
 
     data = tcg_temp_new_i32();
-    tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
+    if (ctx->le_mode) {
+        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_LEUL);
+    } else {
+        tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_BEUL);
+    }
     tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
 
     tcg_temp_free(EA);
@@ -162,7 +166,11 @@  static void gen_lxvdsx(DisasContext *ctx)
     gen_addr_reg_index(ctx, EA);
 
     data = tcg_temp_new_i64();
-    tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
+    if (ctx->le_mode) {
+        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_LEQ);
+    } else {
+        tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_BEQ);
+    }
     tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
 
     tcg_temp_free(EA);