From patchwork Thu May 27 05:21:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 12283357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83085C4707F for ; Thu, 27 May 2021 05:26:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2357B613CC for ; Thu, 27 May 2021 05:26:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2357B613CC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:47342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lm8XK-0008Bi-93 for qemu-devel@archiver.kernel.org; Thu, 27 May 2021 01:26:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lm8Si-0008R7-RU for qemu-devel@nongnu.org; Thu, 27 May 2021 01:21:40 -0400 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:58621) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lm8Sc-00064s-2Z for qemu-devel@nongnu.org; Thu, 27 May 2021 01:21:40 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id CAA1B11D396; Thu, 27 May 2021 14:21:30 +0900 (JST) Received: from yo-satoh-debian.localdomain (y245018.dynamic.ppp.asahi-net.or.jp [118.243.245.18]) by sakura.ysato.name (Postfix) with ESMTPSA id 692871C0077; Thu, 27 May 2021 14:21:30 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 04/11] hw/timer: Remove sh_timer. Date: Thu, 27 May 2021 14:21:15 +0900 Message-Id: <20210527052122.97103-5-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210527052122.97103-1-ysato@users.sourceforge.jp> References: <20210527052122.97103-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Migrate to renesas_timer. Signed-off-by: Yoshinori Sato --- include/hw/timer/tmu012.h | 23 --- hw/timer/sh_timer.c | 368 -------------------------------------- MAINTAINERS | 4 +- hw/timer/Kconfig | 4 - hw/timer/meson.build | 1 - 5 files changed, 2 insertions(+), 398 deletions(-) delete mode 100644 include/hw/timer/tmu012.h delete mode 100644 hw/timer/sh_timer.c diff --git a/include/hw/timer/tmu012.h b/include/hw/timer/tmu012.h deleted file mode 100644 index 808ed8de1d..0000000000 --- a/include/hw/timer/tmu012.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * SuperH Timer - * - * Copyright (c) 2007 Magnus Damm - * - * This code is licensed under the GPL. - */ - -#ifndef HW_TIMER_TMU012_H -#define HW_TIMER_TMU012_H - -#include "exec/hwaddr.h" - -#define TMU012_FEAT_TOCR (1 << 0) -#define TMU012_FEAT_3CHAN (1 << 1) -#define TMU012_FEAT_EXTCLK (1 << 2) - -void tmu012_init(MemoryRegion *sysmem, hwaddr base, - int feat, uint32_t freq, - qemu_irq ch0_irq, qemu_irq ch1_irq, - qemu_irq ch2_irq0, qemu_irq ch2_irq1); - -#endif diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c deleted file mode 100644 index 58af1a1edb..0000000000 --- a/hw/timer/sh_timer.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * SuperH Timer modules. - * - * Copyright (c) 2007 Magnus Damm - * Based on arm_timer.c by Paul Brook - * Copyright (c) 2005-2006 CodeSourcery. - * - * This code is licensed under the GPL. - */ - -#include "qemu/osdep.h" -#include "exec/memory.h" -#include "hw/hw.h" -#include "hw/irq.h" -#include "hw/sh4/sh.h" -#include "hw/timer/tmu012.h" -#include "hw/ptimer.h" - -//#define DEBUG_TIMER - -#define TIMER_TCR_TPSC (7 << 0) -#define TIMER_TCR_CKEG (3 << 3) -#define TIMER_TCR_UNIE (1 << 5) -#define TIMER_TCR_ICPE (3 << 6) -#define TIMER_TCR_UNF (1 << 8) -#define TIMER_TCR_ICPF (1 << 9) -#define TIMER_TCR_RESERVED (0x3f << 10) - -#define TIMER_FEAT_CAPT (1 << 0) -#define TIMER_FEAT_EXTCLK (1 << 1) - -#define OFFSET_TCOR 0 -#define OFFSET_TCNT 1 -#define OFFSET_TCR 2 -#define OFFSET_TCPR 3 - -typedef struct { - ptimer_state *timer; - uint32_t tcnt; - uint32_t tcor; - uint32_t tcr; - uint32_t tcpr; - int freq; - int int_level; - int old_level; - int feat; - int enabled; - qemu_irq irq; -} sh_timer_state; - -/* Check all active timers, and schedule the next timer interrupt. */ - -static void sh_timer_update(sh_timer_state *s) -{ - int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); - - if (new_level != s->old_level) - qemu_set_irq (s->irq, new_level); - - s->old_level = s->int_level; - s->int_level = new_level; -} - -static uint32_t sh_timer_read(void *opaque, hwaddr offset) -{ - sh_timer_state *s = (sh_timer_state *)opaque; - - switch (offset >> 2) { - case OFFSET_TCOR: - return s->tcor; - case OFFSET_TCNT: - return ptimer_get_count(s->timer); - case OFFSET_TCR: - return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); - case OFFSET_TCPR: - if (s->feat & TIMER_FEAT_CAPT) - return s->tcpr; - /* fall through */ - default: - hw_error("sh_timer_read: Bad offset %x\n", (int)offset); - return 0; - } -} - -static void sh_timer_write(void *opaque, hwaddr offset, - uint32_t value) -{ - sh_timer_state *s = (sh_timer_state *)opaque; - int freq; - - switch (offset >> 2) { - case OFFSET_TCOR: - s->tcor = value; - ptimer_transaction_begin(s->timer); - ptimer_set_limit(s->timer, s->tcor, 0); - ptimer_transaction_commit(s->timer); - break; - case OFFSET_TCNT: - s->tcnt = value; - ptimer_transaction_begin(s->timer); - ptimer_set_count(s->timer, s->tcnt); - ptimer_transaction_commit(s->timer); - break; - case OFFSET_TCR: - ptimer_transaction_begin(s->timer); - if (s->enabled) { - /* Pause the timer if it is running. This may cause some - inaccuracy dure to rounding, but avoids a whole lot of other - messyness. */ - ptimer_stop(s->timer); - } - freq = s->freq; - /* ??? Need to recalculate expiry time after changing divisor. */ - switch (value & TIMER_TCR_TPSC) { - case 0: freq >>= 2; break; - case 1: freq >>= 4; break; - case 2: freq >>= 6; break; - case 3: freq >>= 8; break; - case 4: freq >>= 10; break; - case 6: - case 7: - if (s->feat & TIMER_FEAT_EXTCLK) { - break; - } - /* fallthrough */ - default: - hw_error("sh_timer_write: Reserved TPSC value\n"); - } - switch ((value & TIMER_TCR_CKEG) >> 3) { - case 0: - break; - case 1: - case 2: - case 3: - if (s->feat & TIMER_FEAT_EXTCLK) { - break; - } - /* fallthrough */ - default: - hw_error("sh_timer_write: Reserved CKEG value\n"); - } - switch ((value & TIMER_TCR_ICPE) >> 6) { - case 0: - break; - case 2: - case 3: - if (s->feat & TIMER_FEAT_CAPT) { - break; - } - /* fallthrough */ - default: - hw_error("sh_timer_write: Reserved ICPE value\n"); - } - if ((value & TIMER_TCR_UNF) == 0) { - s->int_level = 0; - } - - value &= ~TIMER_TCR_UNF; - - if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { - hw_error("sh_timer_write: Reserved ICPF value\n"); - } - - value &= ~TIMER_TCR_ICPF; /* capture not supported */ - - if (value & TIMER_TCR_RESERVED) { - hw_error("sh_timer_write: Reserved TCR bits set\n"); - } - s->tcr = value; - ptimer_set_limit(s->timer, s->tcor, 0); - ptimer_set_freq(s->timer, freq); - if (s->enabled) { - /* Restart the timer if still enabled. */ - ptimer_run(s->timer, 0); - } - ptimer_transaction_commit(s->timer); - break; - case OFFSET_TCPR: - if (s->feat & TIMER_FEAT_CAPT) { - s->tcpr = value; - break; - } - /* fallthrough */ - default: - hw_error("sh_timer_write: Bad offset %x\n", (int)offset); - } - sh_timer_update(s); -} - -static void sh_timer_start_stop(void *opaque, int enable) -{ - sh_timer_state *s = (sh_timer_state *)opaque; - -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); -#endif - - ptimer_transaction_begin(s->timer); - if (s->enabled && !enable) { - ptimer_stop(s->timer); - } - if (!s->enabled && enable) { - ptimer_run(s->timer, 0); - } - ptimer_transaction_commit(s->timer); - s->enabled = !!enable; - -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop done %d\n", s->enabled); -#endif -} - -static void sh_timer_tick(void *opaque) -{ - sh_timer_state *s = (sh_timer_state *)opaque; - s->int_level = s->enabled; - sh_timer_update(s); -} - -static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) -{ - sh_timer_state *s; - - s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); - s->freq = freq; - s->feat = feat; - s->tcor = 0xffffffff; - s->tcnt = 0xffffffff; - s->tcpr = 0xdeadbeef; - s->tcr = 0; - s->enabled = 0; - s->irq = irq; - - s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); - - sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); - sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); - sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); - sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); - /* ??? Save/restore. */ - return s; -} - -typedef struct { - MemoryRegion iomem; - MemoryRegion iomem_p4; - MemoryRegion iomem_a7; - void *timer[3]; - int level[3]; - uint32_t tocr; - uint32_t tstr; - int feat; -} tmu012_state; - -static uint64_t tmu012_read(void *opaque, hwaddr offset, - unsigned size) -{ - tmu012_state *s = (tmu012_state *)opaque; - -#ifdef DEBUG_TIMER - printf("tmu012_read 0x%lx\n", (unsigned long) offset); -#endif - - if (offset >= 0x20) { - if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); - } - return sh_timer_read(s->timer[2], offset - 0x20); - } - - if (offset >= 0x14) - return sh_timer_read(s->timer[1], offset - 0x14); - - if (offset >= 0x08) - return sh_timer_read(s->timer[0], offset - 0x08); - - if (offset == 4) - return s->tstr; - - if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) - return s->tocr; - - hw_error("tmu012_write: Bad offset %x\n", (int)offset); - return 0; -} - -static void tmu012_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - tmu012_state *s = (tmu012_state *)opaque; - -#ifdef DEBUG_TIMER - printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); -#endif - - if (offset >= 0x20) { - if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); - } - sh_timer_write(s->timer[2], offset - 0x20, value); - return; - } - - if (offset >= 0x14) { - sh_timer_write(s->timer[1], offset - 0x14, value); - return; - } - - if (offset >= 0x08) { - sh_timer_write(s->timer[0], offset - 0x08, value); - return; - } - - if (offset == 4) { - sh_timer_start_stop(s->timer[0], value & (1 << 0)); - sh_timer_start_stop(s->timer[1], value & (1 << 1)); - if (s->feat & TMU012_FEAT_3CHAN) { - sh_timer_start_stop(s->timer[2], value & (1 << 2)); - } else { - if (value & (1 << 2)) { - hw_error("tmu012_write: Bad channel\n"); - } - } - - s->tstr = value; - return; - } - - if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { - s->tocr = value & (1 << 0); - } -} - -static const MemoryRegionOps tmu012_ops = { - .read = tmu012_read, - .write = tmu012_write, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - -void tmu012_init(MemoryRegion *sysmem, hwaddr base, - int feat, uint32_t freq, - qemu_irq ch0_irq, qemu_irq ch1_irq, - qemu_irq ch2_irq0, qemu_irq ch2_irq1) -{ - tmu012_state *s; - int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; - - s = (tmu012_state *)g_malloc0(sizeof(tmu012_state)); - s->feat = feat; - s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); - s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); - if (feat & TMU012_FEAT_3CHAN) { - s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, - ch2_irq0); /* ch2_irq1 not supported */ - } - - memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, - "timer", 0x100000000ULL); - - memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", - &s->iomem, 0, 0x1000); - memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); - - memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", - &s->iomem, 0, 0x1000); - memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); - /* ??? Save/restore. */ -} diff --git a/MAINTAINERS b/MAINTAINERS index ecfa97cefa..4e41c3ff91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1414,7 +1414,7 @@ F: hw/char/renesas_sci.c F: hw/sh4/r2d.c F: hw/intc/sh_intc.c F: hw/pci-host/sh_pci.c -F: hw/timer/sh_timer.c +F: hw/timer/renesas_timer.c F: include/hw/sh4/sh_intc.h Shix @@ -1425,7 +1425,7 @@ F: hw/block/tc58128.c F: hw/char/reness_sci.c F: hw/sh4/shix.c F: hw/intc/sh_intc.c -F: hw/timer/sh_timer.c +F: hw/timer/renesas_timer.c F: include/hw/sh4/sh_intc.h SPARC Machines diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 347add12dd..ec19708a4d 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -36,10 +36,6 @@ config CMSDK_APB_DUALTIMER bool select PTIMER -config SH_TIMER - bool - select PTIMER - config RENESAS_TMR bool diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 9019dce993..ec70821c0b 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -27,7 +27,6 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gptimer.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_synctimer.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c')) -softmmu_ss.add(when: 'CONFIG_SH_TIMER', if_true: files('sh_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))