| Message ID | 20210527170630.43458-1-haozhong@zhan9.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | xio3130_downstream: Set the maximum link width and speed | expand |
On 05/28/21 01:06, Haozhong Zhang wrote: > The current implementation leaves 0 in the maximum link width (MLW) > and speed (MLS) fields of the PCI_EXP_LNKCAP register of a xio3130 > downstream port device. As a consequence, when that downstream port > negotiates the link width and speed with its downstream device, 0 will > be used and filled in the MLW and MLS fields of the PCI_EXP_LNKSTA > register of that downstream port. > > Normally, such 0 MLS and MLW in PCI_EXP_LNKSTA register only make the > guest lspci output looks weird (like "speed unknown" and "x0 width"). > However, it also fails the hot-plug of device to the xio3130 > downstream port. The guest Linux kernel complains: > > pcieport 0000:01:00.0: pciehp: Slot(0): Cannot train link: status 0x2000 > > because the pciehp_hpc driver expects a read of valid (non-zero) MLW > from PCI_EXP_LNKSTA register of that downstream port. > > This patch addresses the above issue by setting MLW and MLS in > PCI_EXP_LNKCAP of the xio3130 downstream port to values defined in its > data manual, i.e., x1 and 2.5 GT respectively. > > Signed-off-by: Haozhong Zhang <zhanghaozhong@bytedance.com> > --- > hw/pci-bridge/xio3130_downstream.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c > index 04aae72cd6..fbf9868ad7 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -87,6 +87,13 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) > goto err_bridge; > } > > + /* > + * Following two fields must be set before calling pcie_cap_init() which > + * will fill them to MLS and MLW of PCI_EXP_LNKCAP register. > + */ > + s->speed = QEMU_PCI_EXP_LNK_2_5GT; > + s->width = QEMU_PCI_EXP_LNK_X1; > + > rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, > p->port, errp); > if (rc < 0) { > -- > 2.31.1 > > Forgot to cc Marcel
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 04aae72cd6..fbf9868ad7 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -87,6 +87,13 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } + /* + * Following two fields must be set before calling pcie_cap_init() which + * will fill them to MLS and MLW of PCI_EXP_LNKCAP register. + */ + s->speed = QEMU_PCI_EXP_LNK_2_5GT; + s->width = QEMU_PCI_EXP_LNK_X1; + rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); if (rc < 0) {
The current implementation leaves 0 in the maximum link width (MLW) and speed (MLS) fields of the PCI_EXP_LNKCAP register of a xio3130 downstream port device. As a consequence, when that downstream port negotiates the link width and speed with its downstream device, 0 will be used and filled in the MLW and MLS fields of the PCI_EXP_LNKSTA register of that downstream port. Normally, such 0 MLS and MLW in PCI_EXP_LNKSTA register only make the guest lspci output looks weird (like "speed unknown" and "x0 width"). However, it also fails the hot-plug of device to the xio3130 downstream port. The guest Linux kernel complains: pcieport 0000:01:00.0: pciehp: Slot(0): Cannot train link: status 0x2000 because the pciehp_hpc driver expects a read of valid (non-zero) MLW from PCI_EXP_LNKSTA register of that downstream port. This patch addresses the above issue by setting MLW and MLS in PCI_EXP_LNKCAP of the xio3130 downstream port to values defined in its data manual, i.e., x1 and 2.5 GT respectively. Signed-off-by: Haozhong Zhang <zhanghaozhong@bytedance.com> --- hw/pci-bridge/xio3130_downstream.c | 7 +++++++ 1 file changed, 7 insertions(+)