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Thu, 27 May 2021 13:06:47 -0400 (EDT) From: Haozhong Zhang To: qemu-devel@nongnu.org Subject: [PATCH] xio3130_downstream: Set the maximum link width and speed Date: Fri, 28 May 2021 01:06:30 +0800 Message-Id: <20210527170630.43458-1-haozhong@zhan9.net> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Received-SPF: pass client-ip=66.111.4.28; envelope-from=haozhong@zhan9.net; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Haozhong Zhang , mst@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The current implementation leaves 0 in the maximum link width (MLW) and speed (MLS) fields of the PCI_EXP_LNKCAP register of a xio3130 downstream port device. As a consequence, when that downstream port negotiates the link width and speed with its downstream device, 0 will be used and filled in the MLW and MLS fields of the PCI_EXP_LNKSTA register of that downstream port. Normally, such 0 MLS and MLW in PCI_EXP_LNKSTA register only make the guest lspci output looks weird (like "speed unknown" and "x0 width"). However, it also fails the hot-plug of device to the xio3130 downstream port. The guest Linux kernel complains: pcieport 0000:01:00.0: pciehp: Slot(0): Cannot train link: status 0x2000 because the pciehp_hpc driver expects a read of valid (non-zero) MLW from PCI_EXP_LNKSTA register of that downstream port. This patch addresses the above issue by setting MLW and MLS in PCI_EXP_LNKCAP of the xio3130 downstream port to values defined in its data manual, i.e., x1 and 2.5 GT respectively. Signed-off-by: Haozhong Zhang --- hw/pci-bridge/xio3130_downstream.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 04aae72cd6..fbf9868ad7 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -87,6 +87,13 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } + /* + * Following two fields must be set before calling pcie_cap_init() which + * will fill them to MLS and MLW of PCI_EXP_LNKCAP register. + */ + s->speed = QEMU_PCI_EXP_LNK_2_5GT; + s->width = QEMU_PCI_EXP_LNK_X1; + rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); if (rc < 0) {