| Message ID | 20210529165443.1114402-1-f4bug@amsat.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/mips: Raise exception when DINSV opcode used with DSP disabled | expand |
On 5/29/21 9:54 AM, Philippe Mathieu-Daudé wrote: > Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, > Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": > > If the Module/ASE is not implemented, executing such an instruction > must cause a Reserved Instruction Exception. > > The DINSV instruction lists the following exceptions: > - Reserved Instruction > - DSP Disabled > > If the MIPS core doesn't support the DSP module, or the DSP is > disabled, do not handle the '$rt = $0' case as a no-op but raise > the proper exception instead. > > Cc: Jia Liu<proljc@gmail.com> > Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") > Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> > --- > target/mips/tcg/translate.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 5/29/21 6:54 PM, Philippe Mathieu-Daudé wrote: > Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, > Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": > > If the Module/ASE is not implemented, executing such an instruction > must cause a Reserved Instruction Exception. > > The DINSV instruction lists the following exceptions: > - Reserved Instruction > - DSP Disabled > > If the MIPS core doesn't support the DSP module, or the DSP is > disabled, do not handle the '$rt = $0' case as a no-op but raise > the proper exception instead. > > Cc: Jia Liu <proljc@gmail.com> > Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/mips/tcg/translate.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Thanks, applied to mips-next.
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c03a8ae1fed..6ccba34c050 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -24373,10 +24373,11 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) { TCGv t0, t1; + check_dsp(ctx); + if (rt == 0) { break; } - check_dsp(ctx); t0 = tcg_temp_new(); t1 = tcg_temp_new();
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu <proljc@gmail.com> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/tcg/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)