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Fri, 04 Jun 2021 09:32:55 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z188sm6319994wme.38.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CDBD01FFC8; Fri, 4 Jun 2021 16:53:18 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 49/99] target/arm: make further preparation for the exception code to move Date: Fri, 4 Jun 2021 16:52:22 +0100 Message-Id: <20210604155312.15902-50-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Claudio Fontana the exception code in tcg/ needs some adjustment before being exposed to KVM-only builds. We need to call arm_rebuild_hflags only when TCG is enabled, or we will error out. The direct call to helper_rebuild_hflags_a64(env, new_el) will not be possible when extracting out to common code, it seems safe to replace it with a call to arm_rebuild_hflags, since the write to pstate is already done. Also, some CONFIG_TCG needs to be extended further, so that all the tcg-only code is marked as such. Signed-off-by: Claudio Fontana Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/tcg/helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index e55209491f..7a9eaec5cb 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -755,7 +755,9 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; - arm_rebuild_hflags(env); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -1242,7 +1244,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); - helper_rebuild_hflags_a64(env, new_el); + + if (tcg_enabled()) { + /* pstate already written, so we can use arm_rebuild_hflags here */ + arm_rebuild_hflags(env); + } env->pc = addr; @@ -1306,6 +1312,7 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } +#ifdef CONFIG_TCG if (arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); @@ -1317,7 +1324,6 @@ void arm_cpu_do_interrupt(CPUState *cs) * that caused the exception, not the target exception level, so * must be handled here. */ -#ifdef CONFIG_TCG if (cs->exception_index == EXCP_SEMIHOST) { handle_semihosting(cs); return;